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    Method and system for providing a variation resistant magnetic junction-based XNOR cell usable in neuromorphic computing
    55.
    发明授权
    Method and system for providing a variation resistant magnetic junction-based XNOR cell usable in neuromorphic computing 有权

    公开(公告)号：US11290110B2

    公开(公告)日：2022-03-29

    申请号：US15886179

    申请日：2018-02-01

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Borna J. Obradovic ,  Titash Rakshit ,  Ryan M. Hatcher ,  Jorge A. Kittl ,  Mark S. Rodder

    IPC: H03K19/21 ,  G06N3/063 ,  H03K19/18

    Abstract: A hardware cell and method for performing a digital XNOR of an input signal and weights are described. The hardware cell includes input lines, a plurality of pairs of magnetic junctions, output transistors and at least one selection transistor coupled with the output transistors. The input lines receive the input signal and its complement. The magnetic junctions store the weight. Each magnetic junction includes a reference layer, a free layer and a nonmagnetic spacer layer between the reference layer and the free layer. The free layer has stable magnetic states and is programmable using spin-transfer torque and/or spin-orbit interaction torque. The first magnetic junction of a pair receives the input signal. The second magnetic junction of the pair receives the input signal complement. The output transistors are coupled with the magnetic junctions such that each pair of magnetic junctions forms a voltage divider. The output transistors form a sense amplifier.

    Composite piezoelectric capacitor
    56.
    发明授权
    Composite piezoelectric capacitor 有权

    公开(公告)号：US11217392B2

    公开(公告)日：2022-01-04

    申请号：US16417346

    申请日：2019-05-20

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Ryan M. Hatcher ,  Titash Rakshit ,  Jorge A. Kittl ,  Joon Goo Hong ,  Dharmendar Palle

    IPC: H01L41/083 ,  H01G4/12 ,  H01L29/51 ,  H01L29/78 ,  H01G4/008

    Abstract: A circuit element. In some embodiments, the circuit element includes a first terminal, a second terminal, and a layered structure. The layered structure may include a first conductive layer connected to the first terminal, a first piezoelectric layer on the first conductive layer, a second piezoelectric layer on the first piezoelectric layer, and a second conductive layer connected to the second terminal. The first piezoelectric layer may have a first piezoelectric tensor and a first permittivity tensor, and the second piezoelectric layer may have a second piezoelectric tensor and a second permittivity tensor, one or both of the second piezoelectric tensor and a second permittivity tensor differing, respectively, from the first piezoelectric tensor and the first permittivity tensor.

    Ferroelectric-based memory cell usable in on-logic chip memory
    59.
    发明授权
    Ferroelectric-based memory cell usable in on-logic chip memory 有权

    公开(公告)号：US10679688B2

    公开(公告)日：2020-06-09

    申请号：US16142954

    申请日：2018-09-26

    Applicant: Samsung Electronics Co., LTD.

    Inventor： Titash Rakshit ,  Borna J. Obradovic ,  Ryan M. Hatcher ,  Jorge A. Kittl

    IPC: G11C11/22 ,  H01L27/11585 ,  H01L27/11502

    Abstract: A memory cell and method for utilizing the memory cell are described. The memory cell includes at least one ferroelectric transistor (FE-transistor) and at least one selection transistor coupled with the FE-transistor. An FE-transistor includes a transistor and a ferroelectric capacitor for storing data. The ferroelectric capacitor includes ferroelectric material(s). In some aspects, the memory cell consists of a FE-transistor and a selection transistor. In some aspects, the transistor of the FE-transistor includes a source, a drain and a gate coupled with the ferroelectric capacitor. In this aspect, the selection transistor includes a selection transistor source, a selection transistor drain and a selection transistor gate. In this aspect, a write port of the memory cell is the selection transistor source or the selection transistor drain. The other of the selection transistor source and drain is coupled to the ferroelectric capacitor.

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