公开(公告)号：US20150325563A1

公开(公告)日：2015-11-12

申请号：US14272981

申请日：2014-05-08

Applicant: QUALCOMM Incorporated

Inventor： Pratyush Kamal ,  Yang Du

IPC: H01L27/02 ,  H01L27/12 ,  H03K3/012 ,  H01L27/092

CPC classification number: H01L27/0207 ,  H01L27/092 ,  H01L27/1203 ,  H01L29/7831 ,  H01L29/78696 ,  H03K3/012

Abstract: Silicon-on-insulator (SOI) complementary metal oxide semiconductor (CMOS) standard library cell circuits having gate back-bias rail(s) are disclosed. Related systems and methods are also disclosed. In one aspect, a SOI CMOS standard library cell circuit is provided that is comprised of one or more standard library cells. Each standard library cell includes one or more PMOS channel regions and one or more NMOS channel regions. Each standard library cell has one or more gate back-bias rails disposed adjacent to PMOS and NMOS channel regions. The gate back-bias rails are configured to apply bias voltages to corresponding PMOS and NMOS channel regions to adjust threshold voltages of PMOS and NMOS transistors associated with the PMOS and NMOS channel regions, respectively. Voltage biasing can be controlled to adjust timing of an IC using SOI CMOS standard library cell circuits to achieve design timing targets without including timing closure elements that consume additional area.

Abstract translation: 公开了具有栅极背偏置导轨的绝缘体上硅（SOI）互补金属氧化物半导体（CMOS）标准库单元电路。 还公开了相关系统和方法。 在一个方面，提供了由一个或多个标准库单元组成的SOI CMOS标准库单元电路。 每个标准库单元包括一个或多个PMOS沟道区和一个或多个NMOS沟道区。 每个标准库单元具有邻近PMOS和NMOS沟道区设置的一个或多个栅极偏置导轨。 栅极反向偏置导轨被配置为向相应的PMOS和NMOS沟道区域施加偏置电压，以分别调整与PMOS和NMOS沟道区相关联的PMOS和NMOS晶体管的阈值电压。 可以控制电压偏置，以调整使用SOI CMOS标准库单元电路的IC的定时，以实现设计时序目标，而不包括消耗额外面积的时序闭合元件。

公开(公告)号：US09147438B2

公开(公告)日：2015-09-29

申请号：US14152248

申请日：2014-01-10

Applicant: QUALCOMM Incorporated

Inventor： Pratyush Kamal ,  Yang Du ,  Kambiz Samadi

IPC: G11C17/00 ,  G11C5/02 ,  H04L12/933 ,  H01L23/00 ,  G06F1/32 ,  H01L27/06

CPC classification number: G11C5/02 ,  G06F1/3225 ,  G06F1/3275 ,  G11C5/025 ,  G11C5/063 ,  H01L24/89 ,  H01L27/0688 ,  H01L2924/1434 ,  H04L49/101 ,  H04L49/109 ,  Y02D10/13 ,  Y02D10/14

Abstract: Monolithic three dimensional (3D) integrated circuits (ICs) (3DICs) with vertical memory components are disclosed. A 3D memory crossbar architecture with tight-pitched vertical monolithic intertier vias (MIVs) for inter-block routing and multiplexers at each tier for block access is used to shorten overall conductor length and reduce resistive-capacitive (RC) delay. Elimination of such long crossbars reduces the RC delay of the crossbar and generally improves performance and speed. Further, elimination of the long horizontal crossbars makes conductor routing easier. The MIVs, with their small run-length, can work without the need for repeaters (unlike the long crossbars), and control logic may be used to configure the memory banks based on use.

Abstract translation: 公开了具有垂直存储器组件的单片三维（3D）集成电路（IC）（3DIC）。 使用具有用于块间路由选择的紧密垂直单片中间层通道（MIV）的三维存储器交叉结构架构，用于块访问的每层级多路复用器，以缩短整体导体长度并降低电阻 - 电容（RC）延迟。 消除这种长的十字准线会降低交叉开关的RC延迟，并通常提高性能和速度。 此外，消除长的横向横梁使得导线布线更容易。 MIVs具有较小的长度，可以在不需要中继器的情况下工作（与长十字准线不同），并且可以使用控制逻辑来基于使用配置存储体。

公开(公告)号：US09123721B2

公开(公告)日：2015-09-01

申请号：US14132098

申请日：2013-12-18

Applicant: QUALCOMM Incorporated

Inventor： Kambiz Samadi ,  Shreepad Amar Panth ,  Pratyush Kamal ,  Yang Du

IPC: H01L21/768 ,  H01L23/522 ,  G06F17/50

CPC classification number: H01L23/5226 ,  G06F17/5072 ,  G06F17/5081 ,  H01L25/0657 ,  H01L27/0688 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Placement of Monolithic Inter-tier Vias (MIVs) within monolithic three dimensional (3D) integrated circuits (ICs) (3DICs) using clustering to increase usable whitespace is disclosed. In one embodiment, a method of placing MIVs in a monolithic 3DIC using clustering is provided. The method comprises determining if any MIV placement clusters are included within a plurality of initial MIV placements of a plurality of MIVs within an initial 3DIC layout plan. The method further comprises aligning each MIV of the plurality of MIVs within each MIV placement cluster in the initial 3DIC layout plan at a final MIV placement for each MIV placement cluster to provide a clustered 3DIC layout plan.

Abstract translation: 公开了使用聚类来增加可用空白位置的单片三维（3D）集成电路（IC）（3DIC）中的单片间通道（MIV））。 在一个实施例中，提供了使用聚类将MIV放置在单片3DIC中的方法。 该方法包括确定在初始3DIC布局图中是否有多个MIV的多个初始MIV布置内是否包括任何MIV布局群集。 该方法还包括在初始3DIC布局图中的每个MIV放置簇内的多个MIV中的每个MIV在每个MIV放置簇的最终MIV放置处对齐以提供聚集的3DIC布局图。

公开(公告)号：US09098666B2

公开(公告)日：2015-08-04

申请号：US13792486

申请日：2013-03-11

Applicant: QUALCOMM Incorporated

Inventor： Kambiz Samadi ,  Shreepad A. Panth ,  Jing Xie ,  Yang Du

IPC: G06F17/50 ,  H01L23/522 ,  G11C5/14 ,  G06F1/32

CPC classification number: G06F17/5072 ,  G06F1/32 ,  G06F1/3287 ,  G06F17/5045 ,  G06F17/505 ,  G06F17/5068 ,  G06F17/5077 ,  G06F2217/62 ,  G11C5/14 ,  H01L23/5226 ,  H01L2924/0002 ,  H03K19/0008 ,  H01L2924/00

Abstract: Exemplary embodiments of the invention are directed to systems and method for designing a clock distribution network for an integrated circuit. The embodiments identify critical sources of clock skew, tightly control the timing of the clock and build that timing into the overall clock distribution network and integrated circuit design. The disclosed embodiments separate the clock distribution network (CDN), i.e., clock generation circuitry, wiring, buffering and registers, from the rest of the logic to improve the clock tree design and reduce the area footprint. In one embodiment, the CDN is separated to a separate tier of a 3D integrated circuit, and the CDN is connected to the logic tier(s) via high-density inter-tier vias. The embodiments are particularly advantageous for implementation with monolithic 3D integrated circuits.

Abstract translation: 本发明的示例性实施例涉及用于设计用于集成电路的时钟分配网络的系统和方法。 这些实施例确定了时钟偏移的关键来源，紧密地控制时钟的定时并将该时序构建到整个时钟分配网络和集成电路设计中。 所公开的实施例将时钟分配网络（CDN），即时钟生成电路，布线，缓冲和寄存器与逻辑的其余部分分开，以改进时钟树设计并减少面积占用。 在一个实施例中，CDN被分离成3D集成电路的单独层，并且CDN通过高密度层间通孔连接到逻辑层。 这些实施例对于使用单片3D集成电路的实现特别有利。

公开(公告)号：US20150145143A1

公开(公告)日：2015-05-28

申请号：US14132098

申请日：2013-12-18

Applicant: QUALCOMM Incorporated

Inventor： Kambiz Samadi ,  Shreepad Amar Panth ,  Pratyush Kamal ,  Yang Du

IPC: H01L23/522 ,  G06F17/50

CPC classification number: H01L23/5226 ,  G06F17/5072 ,  G06F17/5081 ,  H01L25/0657 ,  H01L27/0688 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Placement of Monolithic Inter-tier Vias (MIVs) within monolithic three dimensional (3D) integrated circuits (ICs) (3DICs) using clustering to increase usable whitespace is disclosed. In one embodiment, a method of placing MIVs in a monolithic 3DIC using clustering is provided. The method comprises determining if any MIV placement clusters are included within a plurality of initial MIV placements of a plurality of MIVs within an initial 3DIC layout plan. The method further comprises aligning each MIV of the plurality of MIVs within each MIV placement cluster in the initial 3DIC layout plan at a final MIV placement for each MIV placement cluster to provide a clustered 3DIC layout plan.

Abstract translation: 公开了使用聚类来增加可用空白位置的单片三维（3D）集成电路（IC）（3DIC）中的单片间通道（MIV））。 在一个实施例中，提供了使用聚类将MIV放置在单片3DIC中的方法。 该方法包括确定在初始3DIC布局图中是否有多个MIV的多个初始MIV布置内是否包括任何MIV布局群集。 该方法还包括在初始3DIC布局图中的每个MIV放置簇内的多个MIV中的每个MIV在每个MIV放置簇的最终MIV放置处对齐以提供聚集的3DIC布局图。

公开(公告)号：US08796741B2

公开(公告)日：2014-08-05

申请号：US13644720

申请日：2012-10-04

Applicant: Qualcomm Incorporated

Inventor： Shiqun Gu ,  Yang Du

IPC: H01L27/10

CPC classification number: H01L27/0688 ,  H01L21/2007 ,  H01L21/8258 ,  H01L27/092 ,  H01L29/1606

Abstract: A semiconductor device and methods of making a semiconductor device using graphene are described. A monolithic three dimensional integrated circuit device includes a first layer having first active devices. The monolithic three dimensional integrated circuit device also includes a second layer having second active devices that each include a graphene portion. The second layer can be fabricated on the first layer to form a stack of active devices. A base substrate may support the stack of active devices.

Abstract translation: 描述半导体器件以及使用石墨烯制造半导体器件的方法。 单片三维集成电路器件包括具有第一有源器件的第一层。 单片三维集成电路器件还包括具有第二有源器件的第二层，每个有源器件均包括石墨烯部分。 可以在第一层上制造第二层以形成有源器件的堆叠。 基底可以支撑有源器件的堆叠。

公开(公告)号：US20140146630A1

公开(公告)日：2014-05-29

申请号：US13792592

申请日：2013-03-11

Applicant: QUALCOMM INCORPORATED

Inventor： Jing Xie ,  Yang Du

IPC: G11C5/14 ,  G06F17/50

CPC classification number: G06F17/5072 ,  G06F1/32 ,  G06F1/3287 ,  G06F17/5045 ,  G06F17/505 ,  G06F17/5068 ,  G06F17/5077 ,  G06F2217/62 ,  G11C5/14 ,  H01L23/5226 ,  H01L2924/0002 ,  H03K19/0008 ,  H01L2924/00

Abstract: The disclosed embodiments comprise a multi-stage circuit operating across different power domains. The multi-stage circuit may be implemented as a master-slave flip-flop circuit integrated with a level shifter that transfers data across different power domains. The master and slave stages of the flip-flop may be split across two tiers of a 3D IC and may include (i) a level shifter across different power domain integrated within the flip-flop circuit, (ii) reduced one-state writing delays by a self-induced power collapsing technique, (iii) splitting flip-flop power supplies in different tiers using monolithic 3D IC technology, and (iv) cross power domain data transfer between 3D IC tiers.

Abstract translation: 所公开的实施例包括跨越不同功率域操作的多级电路。 多级电路可以实现为与电平转换器集成的主从触发器电路，其在不同的电源域之间传送数据。 触发器的主级和从属级可以分为三层3D IC的两层，并且可以包括（i）跨越触发器电路中的不同功率域的电平移位器，（ii）减少的一状态写入延迟 通过自感电源塌陷技术，（iii）使用单片3D IC技术分割不同层级的触发器电源，以及（iv）3D IC层之间的跨功率域数据传输。

公开(公告)号：US20140145347A1

公开(公告)日：2014-05-29

申请号：US13792486

申请日：2013-03-11

Applicant: QUALCOMM INCORPORATED

Inventor： Kambiz Samadi ,  Shreepad A. Panth ,  Jing Xie ,  Yang Du

IPC: G06F17/50 ,  H01L23/522

CPC classification number: G06F17/5072 ,  G06F1/32 ,  G06F1/3287 ,  G06F17/5045 ,  G06F17/505 ,  G06F17/5068 ,  G06F17/5077 ,  G06F2217/62 ,  G11C5/14 ,  H01L23/5226 ,  H01L2924/0002 ,  H03K19/0008 ,  H01L2924/00

Abstract: Exemplary embodiments of the invention are directed to systems and method for designing a clock distribution network for an integrated circuit. The embodiments identify critical sources of clock skew, tightly control the timing of the clock and build that timing into the overall clock distribution network and integrated circuit design. The disclosed embodiments separate the clock distribution network (CDN), i.e., clock generation circuitry, wiring, buffering and registers, from the rest of the logic to improve the clock tree design and reduce the area footprint. In one embodiment, the CDN is separated to a separate tier of a 3D integrated circuit, and the CDN is connected to the logic tier(s) via high-density inter-tier vias. The embodiments are particularly advantageous for implementation with monolithic 3D integrated circuits.

Abstract translation: 本发明的示例性实施例涉及用于设计用于集成电路的时钟分配网络的系统和方法。 这些实施例确定了时钟偏移的关键来源，紧密地控制时钟的定时并将该时序构建到整个时钟分配网络和集成电路设计中。 所公开的实施例将时钟分配网络（CDN），即时钟生成电路，布线，缓冲和寄存器与逻辑的其余部分分开，以改进时钟树设计并减少面积占用。 在一个实施例中，CDN被分离成3D集成电路的单独层，并且CDN通过高密度层间通孔连接到逻辑层。 这些实施例对于使用单片3D集成电路的实现特别有利。

公开(公告)号：US11733766B2

公开(公告)日：2023-08-22

申请号：US17840265

申请日：2022-06-14

Applicant: QUALCOMM Incorporated

Inventor： Yu Pu ,  Yang Du

IPC: G06F1/32 ,  G06F1/3287 ,  G06F1/3234 ,  G06F1/3296 ,  G06N3/065 ,  G06N3/045

CPC classification number: G06F1/3287 ,  G06F1/3243 ,  G06F1/3296 ,  G06N3/045 ,  G06N3/065

Abstract: A three-dimensional (3D) ultra-low power neuromorphic accelerator is described. The 3D ultra-low power neuromorphic accelerator includes a power manager as well as multiple tiers. The 3D ultra-low power neuromorphic accelerator also includes multiple cores defined on each tier and coupled to the power manager. Each core includes at least a processing element, a non-volatile memory, and a communications module.

公开(公告)号：US10578497B2

公开(公告)日：2020-03-03

申请号：US15706734

申请日：2017-09-17

Applicant: QUALCOMM Incorporated

Inventor： William Xia ,  Yang Du

IPC: G01K7/01 ,  G01K7/02 ,  G01K3/00

Abstract: Disclosed is a system for measuring temperature in an integrated circuit (IC) device. The system includes a diode-based temperature sensor comprising a first plurality of diodes coupled between a power supply pin of the IC device and a ground pin of the IC device and a second plurality of diodes coupled between the power supply pin and the ground pin, and a voltage sensing circuit configured to detect a voltage difference between the first plurality of diodes and the second plurality of diodes.