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    MULTI-SENSING CHANNELS DESIGN FOR PIXEL COMPENSATION
    52.
    发明申请
    MULTI-SENSING CHANNELS DESIGN FOR PIXEL COMPENSATION 审中-公开

    公开(公告)号：US20190156736A1

    公开(公告)日：2019-05-23

    申请号：US16120332

    申请日：2018-09-03

    Applicant: Novatek Microelectronics Corp.

    Inventor： Jhih-Siou Cheng ,  Tzong-Honge Shieh ,  Ju-Lin Huang

    IPC: G09G3/3208

    Abstract: A driver of a display panel is provided. The driver includes a plurality of sensing channels configured to receive a plurality of sensing signals from the display panel via a plurality of sensing lines and output the sensing signals, the sensing channels are coupled to the sensing lines in an arrangement selected from one of a random arrangement and a normal arrangement. The driver further includes a signal convertor coupled to the sensing channels and configured to receive the sensing signals from the sensing channels in a sequence selected from one of a random sequence and a normal sequence.

    Chip package
    57.
    发明授权
    Chip package 有权
    芯片封装

    公开(公告)号：US09245857B2

    公开(公告)日：2016-01-26

    申请号：US14726613

    申请日：2015-06-01

    Applicant: Novatek Microelectronics Corp.

    Inventor： Jhih-Siou Cheng ,  Tzu-Chiang Lin ,  Chia-En Wu ,  Chun-Yung Cho ,  Cheng-Hung Chen ,  Ju-Lin Huang

    IPC: H01L23/12 ,  H01L23/48 ,  H01L23/52 ,  H01L23/40 ,  H01L23/60 ,  H01L23/538 ,  H01L25/065 ,  H01L23/00 ,  H02H9/02

    CPC classification number: H01L23/60 ,  H01L23/5389 ,  H01L24/17 ,  H01L25/0655 ,  H01L2224/16137 ,  H01L2224/16195 ,  H01L2924/0002 ,  H02H9/02 ,  H05K9/0067 ,  H01L2924/00

    Abstract: A chip package structure includes a package body. The package body includes a core circuit and an electrostatic discharge protection circuit. A first connection terminal electrically is connected to the core circuit. A second connection terminal electrically is connected to the electrostatic discharge protection circuit. A first interconnection structure electrically connected to the electrostatic discharge protection circuit, the second connection terminal and a third connection terminal. A first lead electrically connects the second connection terminal and an external circuit. A second lead electrically connects the first connection terminal and the third connection terminal. The second lead and the first lead are substantially separate.

    Abstract translation: 芯片封装结构包括封装体。 封装体包括核心电路和静电放电保护电路。 第一连接端子电连接到核心电路。 第二连接端子电连接到静电放电保护电路。 电连接到静电放电保护电路的第一互连结构，第二连接端子和第三连接端子。 第一引线将第二连接端子和外部电路电连接。 第二引线电连接第一连接端子和第三连接端子。 第二个领先者和第一个领先者基本上是分开的。

    DRIVING VOLTAGE GENERATOR AND DIGITAL TO ANALOG CONVERTER
    58.
    发明申请
    DRIVING VOLTAGE GENERATOR AND DIGITAL TO ANALOG CONVERTER 审中-公开
    驱动电压发生器和数字到模拟转换器

    公开(公告)号：US20150381197A1

    公开(公告)日：2015-12-31

    申请号：US14845289

    申请日：2015-09-04

    Applicant: Novatek Microelectronics Corp.

    Inventor： Jhih-Siou Cheng ,  Ju-Lin Huang ,  Pang-Chan Hung

    IPC: H03M1/76 ,  G09G3/20

    CPC classification number: H03M1/76 ,  G09G3/2007 ,  G09G3/3291 ,  G09G3/3696 ,  G09G5/02 ,  G09G2310/027 ,  G09G2320/0276 ,  G09G2330/028 ,  H03K3/01 ,  H03M1/66 ,  H03M1/765

    Abstract: A digital to analog converter is disclosed. The invention provides a digital to analog converter (DAC) including a plurality of voltage transmitting switches and a selecting signal decoder. The voltage transmitting switches respectively receive a plurality of input voltages, and output terminals of the voltage transmitting switches are commonly coupled to an output terminal of the digital to analog converter. The selecting signal decoder receives a plurality of selecting signals, and generates a plurality of transmitting enable signals to control the voltage transmitting switches. Wherein only one of the voltage transmitting switches is connected between each of the input voltages and the output terminal of the digital to analog converter.

    Abstract translation: 公开了一种数模转换器。 本发明提供一种包括多个电压发射开关和选择信号解码器的数模转换器（DAC）。 电压发送开关分别接收多个输入电压，电压发送开关的输出端子共同耦合到数模转换器的输出端子。 选择信号解码器接收多个选择信号，并且产生多个发送使能信号以控制电压发送开关。 其中只有一个电压发射开关连接在每个输入电压和数模转换器的输出端之间。

    Operational amplifier circuit and method for enhancing driving capacity thereof
    59.
    发明授权
    Operational amplifier circuit and method for enhancing driving capacity thereof 有权
    运算放大器电路及其驱动能力的提高方法

    公开(公告)号：US09106189B2

    公开(公告)日：2015-08-11

    申请号：US14016136

    申请日：2013-09-02

    Applicant: Novatek Microelectronics Corp.

    Inventor： Chieh-An Lin ,  Chun-Yung Cho ,  Ju-Lin Huang

    IPC: H03F3/45 ,  H03F3/30

    CPC classification number: H03F3/45076 ,  H03F3/3022 ,  H03F3/45192 ,  H03F2200/234 ,  H03F2203/45116

    Abstract: An operational amplifier circuit configured to drive a load is provided. The operational amplifier circuit includes an output stage module. The output stage module includes a detection circuit and an output stage circuit. The detection circuit is configured to detect a current output voltage and a previous output voltage based on a comparison result of a current input voltage and the current output voltage. The detection circuit enhances a charge capacity or a discharge capacity of the output stage circuit for the load based on a detection result. Furthermore, a method for enhancing the driving capacity of the operational amplifier circuit is also provided.

    Abstract translation: 提供了构造成驱动负载的运算放大器电路。 运算放大器电路包括输出级模块。 输出级模块包括检测电路和输出级电路。 检测电路被配置为基于当前输入电压和电流输出电压的比较结果来检测电流输出电压和先前的输出电压。 检测电路基于检测结果增强负载的输出级电路的充电容量或放电容量。 此外，还提供了一种用于增强运算放大器电路的驱动能力的方法。

    Driving circuit
    60.
    发明授权
    Driving circuit 有权
    驱动电路

    公开(公告)号：US08797201B2

    公开(公告)日：2014-08-05

    申请号：US13925849

    申请日：2013-06-25

    Applicant: Novatek Microelectronics Corp.

    Inventor： Ju-Lin Huang ,  Jhih-Siou Cheng ,  Chun-Yung Cho ,  Chieh-An Lin

    IPC: H03M1/66

    CPC classification number: H03M1/06 ,  G09G3/20 ,  G09G2300/0421 ,  G09G2310/027 ,  G09G2310/0275 ,  G09G2320/0276 ,  H03M1/66 ,  H03M1/765

    Abstract: A driving circuit includes a plurality of reference voltage lines and a digital to analog converter. The reference voltage lines are configured for respectively transmitting different grayscale reference voltages, in which the grayscale reference voltages are divided into at least two groups, and the wire diameter/wire width of at least one reference voltage line among the reference voltage lines of a first voltage group among the at least two groups is different from the wire diameters/wire widths of the reference voltage lines of a second voltage group among the at least two groups. The digital to analog converter is coupled to the reference voltage lines to receive the grayscale reference voltages and is for converting a digital signal into a grayscale voltage according to the grayscale reference voltages.

    Abstract translation: 驱动电路包括多个参考电压线和数模转换器。 参考电压线被配置为分别传输不同的灰度参考电压，其中灰度参考电压被划分为至少两组，并且第一个参考电压的参考电压线中的至少一个参考电压线的线径/线宽 所述至少两组中的电压组与所述至少两组中的第二电压组的参考电压线的线径/线宽不同。 数模转换器耦合到参考电压线以接收灰度参考电压，并且用于根据灰度参考电压将数字信号转换成灰度级电压。

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