公开(公告)号：US20150311701A1

公开(公告)日：2015-10-29

申请号：US14261195

申请日：2014-04-24

Applicant: General Electric Company

Inventor： Avinash Srikrishnan Kashyap ,  Peter Micah Sandvik ,  Joe Walter Kirstein ,  Alexander Viktorovich Bolotnikov

IPC: H02H9/04 ,  H01L21/768 ,  H01L25/065 ,  H01L29/16 ,  H01L27/02 ,  H01L29/66 ,  H01L21/02 ,  H01L25/00

CPC classification number: H02H9/04 ,  G01R1/0458 ,  G01R31/2642 ,  G01R31/2874 ,  G01R31/2875 ,  G01R31/2891 ,  H01L21/02378 ,  H01L21/02529 ,  H01L21/76898 ,  H01L25/0657 ,  H01L25/50 ,  H01L27/0255 ,  H01L29/1608 ,  H01L29/423 ,  H01L29/42304 ,  H01L29/70 ,  H01L29/732 ,  H01L2225/06541 ,  H01L2924/0002 ,  H02H9/044 ,  H01L2924/00

Abstract: A transient voltage suppression (TVS) device and a method of forming the device are provided. The transient voltage suppression (TVS) device includes a first layer of wide band gap semiconductor material formed of a first conductivity type material, a second layer of wide band gap semiconductor material formed of a second conductivity type material over at least a portion of the first layer, and a third layer of wide band gap semiconductor material formed of the first conductivity type material over at least a portion of the second layer. The TVS device also includes a conductive path electrically coupled between the second layer and an electrical connection to a circuit external to the TVS device, the conductive path configured to permit controlling a turning on of the TVS device at less than a breakdown voltage of the TVS device.

Abstract translation: 提供瞬态电压抑制（TVS）装置和形成装置的方法。 瞬态电压抑制（TVS）器件包括由第一导电类型材料形成的第一层宽带隙半导体材料，第二层宽带隙半导体材料，由第二导电类型材料形成，在第一导电类型材料的至少一部分上形成 层，以及在第二层的至少一部分上由第一导电类型材料形成的第三层宽带隙半导体材料。 TVS设备还包括电耦合在第二层和与TVS设备外部的电路的电连接的导电路径，导电路径被配置为允许以小于TVS的击穿电压来控制TVS设备的接通 设备。

公开(公告)号：US12191384B2

公开(公告)日：2025-01-07

申请号：US17338337

申请日：2021-06-03

Applicant: General Electric Company

Inventor： Stephen Daley Arthur ,  Alexander Viktorovich Bolotnikov ,  Reza Ghandi ,  David Alan Lilienfeld ,  Peter Almern Losee

IPC: H01L29/78 ,  H01L21/04 ,  H01L29/08 ,  H01L29/10 ,  H01L29/16 ,  H01L29/66

Abstract: A charge balanced (CB) trench-metal-oxide-semiconductor field-effect transistor (MOSFET) device may include a charge balanced (CB) layer defined within a first epitaxial (epi) layer that has a first conductivity type. The CB layer may include charge balanced (CB) regions that has a second conductivity type. The CB trench-MOSFET device may include a device layer defined in a second epi layer and having the first conductivity type, where the device layer is disposed on the CB layer. The device layer may include a source region, a base region, a trench feature, and a shield region having the second conductivity type disposed at a bottom surface of the trench feature. The device layer may also include a charge balanced (CB) bus region having the second conductivity type that extends between and electrically couples the CB regions of the CB layer to at least one region of the device layer having the second conductivity type.

公开(公告)号：US11764257B2

公开(公告)日：2023-09-19

申请号：US17572274

申请日：2022-01-10

Applicant: General Electric Company

Inventor： Stephen Daley Arthur ,  Victor Mario Torres ,  Michael J. Hartig ,  Reza Ghandi ,  David Alan Lilienfeld ,  Alexander Viktorovich Bolotnikov

IPC: H01L29/15 ,  H01L31/0312 ,  H01L29/06 ,  H01L29/16 ,  H01L21/04 ,  H01L29/66

CPC classification number: H01L29/0634 ,  H01L21/0465 ,  H01L29/0619 ,  H01L29/0623 ,  H01L29/1608 ,  H01L29/66068

Abstract: A disclosed super-junction (SJ) device includes a first epitaxial (epi) layer that forms a first SJ layer of the SJ device, and includes a second epi layer disposed on the first SJ layer that forms a device layer of the SJ device. An active area of the first and second epi layers includes a first set of SJ pillars comprising a particular doping concentration of a first conductivity type and a second set of SJ pillars comprising the particular doping concentration of a second conductivity type. A termination area of the first and second epi layers has a minimized epi doping concentration of the first conductivity type that is less than the particular doping concentration, and the termination area of the second epi layer includes a plurality of floating regions of the second conductivity type that form a junction termination of the SJ device.

公开(公告)号：US11056586B2

公开(公告)日：2021-07-06

申请号：US16147216

申请日：2018-09-28

Applicant: General Electric Company

Inventor： Stephen Daley Arthur ,  Alexander Viktorovich Bolotnikov ,  Reza Ghandi ,  David Alan Lilienfeld ,  Peter Almem Losee

IPC: H01L29/78 ,  H01L29/10 ,  H01L29/66 ,  H01L29/16 ,  H01L21/04 ,  H01L29/08

Abstract: A charge balanced (CB) trench-metal-oxide-semiconductor field-effect transistor (MOSFET) device may include a charge balanced (CB) layer defined within a first epitaxial (epi) layer that has a first conductivity type. The CB layer may include charge balanced (CB) regions that has a second conductivity type. The CB trench-MOSFET device may include a device layer defined in a second epi layer and having the first conductivity type, where the device layer is disposed on the CB layer. The device layer may include a source region, a base region, a trench feature, and a shield region having the second conductivity type disposed at a bottom surface of the trench feature. The device layer may also include a charge balanced (CB) bus region having the second conductivity type that extends between and electrically couples the CB regions of the CB layer to at least one region of the device layer having the second conductivity type.

公开(公告)号：US11031472B2

公开(公告)日：2021-06-08

申请号：US16282145

申请日：2019-02-21

Applicant: General Electric Company

Inventor： Peter Almern Losee ,  Reza Ghandi ,  Alexander Viktorovich Bolotnikov

IPC: H01L29/15 ,  H01L29/16 ,  H01L29/06 ,  H01L29/78 ,  H01L29/66

Abstract: A silicon carbide (SiC) semiconductor device may include a CB layer defined in a first epitaxial (epi) layer having a first conductivity type. The CB layer may include a plurality of CB regions having a second conductivity type. The SiC semiconductor device may further include a device epi layer having the first conductivity type disposed on the CB layer. The device epi layer may include a plurality of regions having the second conductivity type. Additionally, the SiC semiconductor device may include an ohmic contact disposed on the device epi layer and a rectifying contact disposed on the device epi layer. A field-effect transistor (FET) of the device may include the ohmic contact, and a diode of the device may include the rectifying contact, where the diode and the FET are integrated in the device.

公开(公告)号：US20200212182A1

公开(公告)日：2020-07-02

申请号：US16282145

申请日：2019-02-21

Applicant: General Electric Company

Inventor： Peter Almern Losee ,  Reza Ghandi ,  Alexander Viktorovich Bolotnikov

IPC: H01L29/16 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78

Abstract: A silicon carbide (SiC) semiconductor device may include a CB layer defined in a first epitaxial (epi) layer having a first conductivity type. The CB layer may include a plurality of CB regions having a second conductivity type. The SiC semiconductor device may further include a device epi layer having the first conductivity type disposed on the CB layer. The device epi layer may include a plurality of regions having the second conductivity type. Additionally, the SiC semiconductor device may include an ohmic contact disposed on the device epi layer and a rectifying contact disposed on the device epi layer. A field-effect transistor (FET) of the device may include the ohmic contact, and a diode of the device may include the rectifying contact, where the diode and the FET are integrated in the device.

公开(公告)号：US10608079B2

公开(公告)日：2020-03-31

申请号：US15890077

申请日：2018-02-06

Applicant: General Electric Company

Inventor： Reza Ghandi ,  David Alan Lilienfeld ,  Alexander Viktorovich Bolotnikov ,  Peter Almern Losee

IPC: H01L29/06 ,  H01L29/16 ,  H01L21/02 ,  H01L27/092 ,  H01L21/265 ,  H01L21/324 ,  H01L27/088 ,  H01L21/761 ,  H01L21/82 ,  H01L27/06 ,  H01L21/8234

Abstract: An integrated circuit includes a silicon carbide (SiC) epitaxial layer disposed on a SiC layer, wherein the SiC epitaxial layer has a first conductivity-type and the SiC layer has a second conductivity-type that is opposite to the first conductivity-type. The integrated circuit also includes a junction isolation feature disposed in the SiC epitaxial layer and having the second conductivity-type. The junction isolation feature extends vertically through a thickness of the SiC epitaxial layer and contacts the SiC layer, and wherein the junction isolation feature has a depth of at least about 2 micrometers (μm).

公开(公告)号：US10600649B2

公开(公告)日：2020-03-24

申请号：US15953037

申请日：2018-04-13

Applicant: General Electric Company

Inventor： Alexander Viktorovich Bolotnikov ,  Peter Almern Losee ,  Reza Ghandi ,  David Alan Lilienfeld

IPC: H01L21/04 ,  H01L29/36 ,  H01L29/06 ,  H01L29/78 ,  H01L29/66 ,  H01L29/16 ,  H01L29/10

Abstract: A method of manufacturing a semiconductor device including performing a first implantation in a semiconductor layer via ion implantation forming a first implantation region and performing a second implantation in the semiconductor layer via ion implantation forming a second implantation region. The first and second implantation overlap with one another and combine to form a connection region extending into the semiconductor layer by a predefined depth.

公开(公告)号：US10586846B2

公开(公告)日：2020-03-10

申请号：US16010531

申请日：2018-06-18

Applicant: General Electric Company

Inventor： Alexander Viktorovich Bolotnikov ,  Reza Ghandi ,  David Alan Lilienfeld ,  Peter Almern Losee

IPC: H01L29/06 ,  H01L29/16 ,  H01L21/04 ,  H01L21/265 ,  H01L29/20 ,  H01L21/266 ,  H01L29/78

Abstract: The subject matter disclosed herein relates to super-junction (SJ) power devices and, more specifically, to edge termination techniques for SJ power devices. A semiconductor super-junction (SJ) device includes one or more epitaxial (epi) layers having a termination region disposed adjacent to an active region. The termination region includes a plurality of vertical pillars of a first and a second conductivity-type, wherein, moving outward from the active region, a respective width of each successive vertical pillar is the same or smaller. The termination region also includes a plurality of compensated regions having a low doping concentration disposed directly between a first side of each vertical pillar of the first conductivity-type and a first side of each vertical pillar of the second conductivity-type, wherein, moving outward from the active region, a respective width of each successive compensated region is the same or greater.

公开(公告)号：US10541338B2

公开(公告)日：2020-01-21

申请号：US16060549

申请日：2015-12-15

Applicant: GENERAL ELECTRIC COMPANY

Inventor： Alexander Viktorovich Bolotnikov ,  Peter Almern Losee ,  David Alan Lilienfeld ,  James Jay McMahon

IPC: H01L29/872 ,  H01L29/66 ,  H01L29/36 ,  H01L29/16 ,  H01L29/06 ,  H01L29/167

Abstract: The subject matter disclosed herein relates to silicon carbide (SiC) power devices and, more specifically, to SiC super-junction (SJ) power devices. A SiC-SJ device includes a plurality of SiC semiconductor layers of a first conductivity-type, wherein a first and a second SiC semiconductor layer of the plurality of SiC semiconductor layers comprise a termination region disposed adjacent to an active region with an interface formed therebetween, an act wherein the termination region of the first and the second SiC semiconductor layers comprises a plurality of implanted regions of a second conductivity-type, and wherein an effective doping profile of the termination region of the first SiC semiconductor layer is different from an effective doping profile of the termination region of the second SiC semiconductor layer.