知搜-全球专利检索

  1. 登录
  2. 注册

搜索结果

106 条记录 (耗时 0.033 秒)

    Lateral PNP bipolar transistor with narrow trench emitter
    51.
    发明授权
    Lateral PNP bipolar transistor with narrow trench emitter 有权
    具有窄沟槽发射极的横向PNP双极晶体管

    公开(公告)号：US09312335B2

    公开(公告)日：2016-04-12

    申请号：US13242970

    申请日：2011-09-23

    申请人： Shekar Mallikarjunaswamy ,  François Hébert

    发明人： Shekar Mallikarjunaswamy ,  François Hébert

    IPC分类号： H01L21/331 ,  H01L29/08 ,  H01L29/735 ,  H01L29/66

    CPC分类号： H01L29/6625 ,  H01L21/02532 ,  H01L21/02595 ,  H01L21/2254 ,  H01L21/31111 ,  H01L21/324 ,  H01L21/76224 ,  H01L29/0649 ,  H01L29/0808 ,  H01L29/735

    摘要： A lateral bipolar transistor includes trench emitter and trench collector regions to form ultra-narrow emitter regions, thereby improving emitter efficiency. The same trench process is used to form the emitter/collector trenches as well as the trench isolation structures so that no additional processing steps are needed to form the trench emitter and collector. In embodiments of the present invention, the trench emitter and trench collector regions may be formed using ion implantation into trenches formed in a semiconductor layer. In other embodiments, the trench emitter and trench collector regions may be formed by out-diffusion of dopants from heavily doped polysilicon filled trenches.

    摘要翻译： 横向双极晶体管包括沟槽发射极和沟槽集电极区域，以形成超窄的发射极区域，从而提高发射极效率。 使用相同的沟槽工艺来形成发射极/集电极沟槽以及沟槽隔离结构，使得不需要额外的处理步骤来形成沟槽发射极和集电极。 在本发明的实施例中，可以使用离子注入形成在半导体层中的沟槽中形成沟槽发射极和沟槽集电极区域。 在其他实施例中，沟槽发射极和沟槽集电极区域可以通过从重掺杂的多晶硅填充的沟槽中的掺杂剂的扩散而形成。

    Charged balanced devices with shielded gate trench
    53.
    发明授权
    Charged balanced devices with shielded gate trench 有权
    带屏蔽栅极沟槽的均衡器件

    公开(公告)号：US08860130B2

    公开(公告)日：2014-10-14

    申请号：US13669267

    申请日：2012-11-05

    申请人： François Hébert

    发明人： François Hébert

    IPC分类号： H01L21/336

    CPC分类号： H01L29/7813 ,  H01L21/26586 ,  H01L29/0623 ,  H01L29/0634 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/41766 ,  H01L29/4238 ,  H01L29/66727 ,  H01L29/66734

    摘要： This invention discloses a semiconductor power device disposed on a semiconductor substrate includes a plurality of deep trenches with an epitaxial layer filling said deep trenches and a simultaneously grown top epitaxial layer covering areas above top surface of said deep trenches over the semiconductor substrate. A plurality of trench MOSFET cells disposed in said top epitaxial layer with the top epitaxial layer functioning as the body region and the semiconductor substrate acting as the drain region whereby a super-junction effect is achieved through charge balance between the epitaxial layer in the deep trenches and regions in the semiconductor substrate laterally adjacent to the deep trenches. Each of the trench MOSFET cells further includes a trench gate and a gate-shielding dopant region disposed below and substantially aligned with each of the trench gates for each of the trench MOSFET cells for shielding the trench gate during a voltage breakdown.

    摘要翻译： 本发明公开了一种设置在半导体衬底上的半导体功率器件，包括具有填充所述深沟槽的外延层的多个深沟槽和覆盖半导体衬底上的所述深沟槽顶表面上方的区域的同时生长的顶部外延层。 设置在所述顶部外延层中的多个沟槽MOSFET单元，顶部外延层用作体区，并且半导体衬底用作漏极区域，由此通过深沟槽中的外延层之间的电荷平衡实现超结效应 以及半导体衬底中与深沟槽横向相邻的区域。 每个沟槽MOSFET单元还包括沟槽栅极和栅极屏蔽掺杂剂区域，其设置在用于每个沟槽MOSFET单元的每个沟槽栅极的下方并基本对齐，用于在电压击穿期间屏蔽沟槽栅极。

    Configuration of high-voltage semiconductor power device to achieve three dimensional charge coupling
    54.
    发明授权
    Configuration of high-voltage semiconductor power device to achieve three dimensional charge coupling 有权
    配置高压半导体功率器件实现三维电荷耦合

    公开(公告)号：US08461004B2

    公开(公告)日：2013-06-11

    申请号：US13066373

    申请日：2011-04-12

    申请人： François Hébert ,  Tao Feng

    发明人： François Hébert ,  Tao Feng

    IPC分类号： H01L21/336

    CPC分类号： H01L29/7802 ,  H01L29/0653 ,  H01L29/66712 ,  H01L29/7395 ,  H01L29/7803 ,  H01L29/861 ,  H01L29/872

    摘要： This invention discloses semiconductor device that includes a top region and a bottom region with an intermediate region disposed between said top region and said bottom region with a controllable current path traversing through the intermediate region. The semiconductor device further includes a trench with padded with insulation layer on sidewalls extended from the top region through the intermediate region toward the bottom region wherein the trench includes randomly and substantially uniformly distributed nano-nodules as charge-islands in contact with a drain region below the trench for electrically coupling with the intermediate region for continuously and uniformly distributing a voltage drop through the current path.

    摘要翻译： 本发明公开了一种半导体器件，其包括顶部区域和底部区域，其中间区域设置在所述顶部区域和所述底部区域之间，并具有穿过所述中间区域的可控电流通路。 所述半导体器件还包括沟槽，该沟槽在从所述顶部区域延伸穿过所述中间区域朝向所述底部区域的侧壁上被填充有绝缘层，其中所述沟槽包括随机均匀分布的纳米结节，作为与下面的漏极区域接触的电荷岛 用于与中间区域电耦合的沟槽，用于通过电流路径连续均匀地分配电压降。

    INVERTED-TRENCH GROUNDED-SOURCE FET STRUCTURE USING CONDUCTIVE SUBSTRATES, WITH HIGHLY DOPED SUBSTRATES
    56.
    发明申请
    INVERTED-TRENCH GROUNDED-SOURCE FET STRUCTURE USING CONDUCTIVE SUBSTRATES, WITH HIGHLY DOPED SUBSTRATES 有权
    使用导电基板的反相接地源FET结构，具有高度掺杂的基板

    公开(公告)号：US20120282746A1

    公开(公告)日：2012-11-08

    申请号：US13553152

    申请日：2012-07-19

    申请人： François Hébert

    发明人： François Hébert

    IPC分类号： H01L21/336

    CPC分类号： H01L21/26586 ,  H01L29/0865 ,  H01L29/0878 ,  H01L29/0886 ,  H01L29/407 ,  H01L29/4175 ,  H01L29/4236 ,  H01L29/66689 ,  H01L29/66704 ,  H01L29/66719 ,  H01L29/66734 ,  H01L29/781 ,  H01L29/7811 ,  H01L29/7825

    摘要： This invention discloses an inverted field-effect-transistor (iT-FET) semiconductor device that includes a source disposed on a bottom and a drain disposed on a top of a semiconductor substrate. The semiconductor power device further comprises a trench-sidewall gate placed on sidewalls at a lower portion of a vertical trench surrounded by a body region encompassing a source region with a low resistivity body-source structure connected to a bottom source electrode and a drain link region disposed on top of said body regions thus constituting a drift region. The drift region is operated with a floating potential said iT-FET device achieving a self-termination.

    摘要翻译： 本发明公开了一种反相场效应晶体管（iT-FET）半导体器件，其包括设置在半导体衬底顶部的底部的源极和漏极。 该半导体功率器件还包括一个沟槽侧壁栅极，该沟槽侧壁栅极位于垂直沟槽的下部的侧壁上，该垂直沟槽被包围源极区域的主体区域围绕，该源区域具有连接到底部源极电极和漏极连接区域的低电阻率主体 - 设置在所述身体区域的顶部，从而构成漂移区域。 漂移区域以浮动电位工作，所述iT-FET器件实现自终止。

    Inverted-trench grounded-source FET structure using conductive substrates, with highly doped substrates
    57.
    发明授权
    Inverted-trench grounded-source FET structure using conductive substrates, with highly doped substrates 有权
    使用导电衬底的反向沟槽接地源FET结构，具有高度掺杂的衬底

    公开(公告)号：US08227315B2

    公开(公告)日：2012-07-24

    申请号：US13200867

    申请日：2011-10-04

    申请人： François Hébert

    发明人： François Hébert

    IPC分类号： H01L21/336

    CPC分类号： H01L21/26586 ,  H01L29/0865 ,  H01L29/0878 ,  H01L29/0886 ,  H01L29/407 ,  H01L29/4175 ,  H01L29/4236 ,  H01L29/66689 ,  H01L29/66704 ,  H01L29/66719 ,  H01L29/66734 ,  H01L29/781 ,  H01L29/7811 ,  H01L29/7825

    摘要： This invention discloses an inverted field-effect-transistor (iT-FET) semiconductor device that includes a source disposed on a bottom and a drain disposed on a top of a semiconductor substrate. The semiconductor power device further comprises a trench-sidewall gate placed on sidewalls at a lower portion of a vertical trench surrounded by a body region encompassing a source region with a low resistivity body-source structure connected to a bottom source electrode and a drain link region disposed on top of said body regions thus constituting a drift region. The drift region is operated with a floating potential said iT-FET device achieving a self-termination.

    摘要翻译： 本发明公开了一种反相场效应晶体管（iT-FET）半导体器件，其包括设置在半导体衬底顶部的底部的源极和漏极。 该半导体功率器件还包括一个沟槽侧壁栅极，该沟槽侧壁栅极位于垂直沟槽的下部的侧壁上，该垂直沟槽被包围源极区域的主体区域围绕，该源区域具有连接到底部源极电极和漏极连接区域的低电阻率主体 - 设置在所述身体区域的顶部，从而构成漂移区域。 漂移区域以浮动电位工作，所述iT-FET器件实现自终止。

    Inverted-trench grounded-source FET structure using conductive substrates, with highly doped substrates
    58.
    发明授权
    Inverted-trench grounded-source FET structure using conductive substrates, with highly doped substrates 有权
    使用导电衬底的反向沟槽接地源FET结构，具有高度掺杂的衬底

    公开(公告)号：US08053834B2

    公开(公告)日：2011-11-08

    申请号：US12653354

    申请日：2009-12-11

    申请人： François Hébert

    发明人： François Hébert

    IPC分类号： H01L29/06

    CPC分类号： H01L21/26586 ,  H01L29/0865 ,  H01L29/0878 ,  H01L29/0886 ,  H01L29/407 ,  H01L29/4175 ,  H01L29/4236 ,  H01L29/66689 ,  H01L29/66704 ,  H01L29/66719 ,  H01L29/66734 ,  H01L29/781 ,  H01L29/7811 ,  H01L29/7825

    摘要： This invention discloses an inverted field-effect-transistor (iT-FET) semiconductor device that includes a source disposed on a bottom and a drain disposed on a top of a semiconductor substrate. The semiconductor power device further comprises a trench-sidewall gate placed on sidewalls at a lower portion of a vertical trench surrounded by a body region encompassing a source region with a low resistivity body-source structure connected to a bottom source electrode and a drain link region disposed on top of said body regions thus constituting a drift region. The drift region is operated with a floating potential said iT-FET device achieving a self-termination.

    摘要翻译： 本发明公开了一种反相场效应晶体管（iT-FET）半导体器件，其包括设置在半导体衬底顶部的底部的源极和漏极。 该半导体功率器件还包括一个沟槽侧壁栅极，该沟槽侧壁栅极位于垂直沟槽的下部的侧壁上，该垂直沟槽被包围源极区域的主体区域围绕，该源区域具有连接到底部源极电极和漏极连接区域的低电阻率主体 - 设置在所述身体区域的顶部，从而构成漂移区域。 漂移区域以浮动电位工作，所述iT-FET器件实现自终止。

    Planar grooved power inductor structure and method
    60.
    发明授权
    Planar grooved power inductor structure and method 有权
    平面沟槽功率电感结构及方法

    公开(公告)号：US07971340B2

    公开(公告)日：2011-07-05

    申请号：US13007551

    申请日：2011-01-14

    申请人： François Hébert ,  Tao Feng ,  Jun Lu

    发明人： François Hébert ,  Tao Feng ,  Jun Lu

    IPC分类号： H01F7/02

    CPC分类号： H01F17/0033 ,  H01F1/344 ,  H01F41/046 ,  H01F2017/002 ,  Y10T29/4902

    摘要： An inductor may include a planar ferrite core. A first group of one or more grooves is formed in a first side of the ferrite core. A second group of two or more grooves is formed in a second side of the ferrite core. The grooves in the first and second groups are oriented such that each groove in the first group overlaps with two corresponding grooves in the second group. A first plurality of vias communicates through the ferrite core between the first and second sides of the ferrite core. Each via is located where a groove in the first group overlaps with a groove in the second group. A conductive material is disposed in the first and second groups of grooves and in the vias to form an inductor coil.

    摘要翻译： 电感器可以包括平面铁氧体磁芯。 第一组一个或多个凹槽形成在铁氧体磁芯的第一侧。 在铁氧体磁芯的第二侧形成有第二组两个或多个凹槽。 第一组和第二组中的凹槽被定向成使得第一组中的每个凹槽与第二组中的两个相应的凹槽重叠。 第一多个通孔在铁氧体磁芯的第一和第二侧之间通过铁氧体磁芯连通。 每个通孔位于第一组中的凹槽与第二组中的凹槽重叠的位置。 导电材料设置在第一和第二组沟槽和通孔中以形成电感线圈。