公开(公告)号：US10235953B2

公开(公告)日：2019-03-19

申请号：US15893994

申请日：2018-02-12

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Pan Li ,  Wenbo Li

IPC: G09G3/36 ,  G02F1/13363

Abstract: The present invention discloses a display panel, a displayer and the drive method thereof, the display panel comprising a cell substrate and an array substrate. The array substrate comprises a plurality of gate lines and a plurality of data lines, wherein, a sub-pixel unit is defined by an i-th line gate line, an (i+1)-th line gate line, a j-th column data line and aj+1-th column data line, wherein, i and j are both natural number. The outermost side of the cell substrate is provided with an FPR film array comprising a first FPR film and a second FPR film, wherein, the first FPR film is corresponding to the first pixel electrode so as to convert emitting light of the first pixel electrode into polarized light in a first direction, and the second FPR film is corresponding to the second pixel electrode so as to convert emitting light of the second pixel electrode into polarized light in a second direction, wherein, the first direction is different from the second direction. The displayer shows the original images as well as the interference image at the same time, thereby the original image shown in the displayer cannot be seen and the display information in displayer is protected effectively.

公开(公告)号：US10147744B2

公开(公告)日：2018-12-04

申请号：US15525622

申请日：2016-06-03

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Hongfei Cheng ,  Jianbo Xian ,  Pan Li ,  Xueguang Hao

IPC: H01L27/12 ,  G02F1/1362 ,  G02F1/1368 ,  H01L27/32 ,  H01L29/786 ,  H01L33/00 ,  H01L51/52

Abstract: An array substrate, a method of manufacturing the same, and a display device are provided. In the array substrate of the present disclosure, the gate cutout is formed in the area where the gate line intersects the data line. The array substrate can reduce the coupling capacitance between the data line and the gate line. When the gate cutout extends beyond the area between the first thin film transistor and the second thin film transistor, the mutual interference between two thin film transistors of each pixel region can be further reduced.

公开(公告)号：US10078251B2

公开(公告)日：2018-09-18

申请号：US15308400

申请日：2015-11-02

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Wenbo Li ,  Pan Li

IPC: H01L29/04 ,  G02F1/1362 ,  G02F1/1368 ,  G02F1/1343

CPC classification number: G02F1/13624 ,  G02F1/134309 ,  G02F1/136227 ,  G02F1/136286 ,  G02F1/1368 ,  G02F2001/134345 ,  G02F2201/122 ,  G02F2201/123 ,  G09G3/3648 ,  G09G2320/028

Abstract: An array substrate and a display apparatus are provided according to embodiments of the disclosure. A pixel unit includes a first sub-pixel electrode and a second sub-pixel electrode, the first sub-pixel electrode is connected to a drain of the first TFT, and the second sub-pixel electrode is connected to a drain of the second TFT, a resistance between a source of the first TFT and the data line connected to the first TFT is greater than a resistance between a source of the second TFT and the data line connected to the second TFT, and/or, a resistance between the drain of the first TFT and the first sub-pixel electrode is greater than a resistance between the drain of the second TFT and the second sub-pixel electrode.

公开(公告)号：US09977300B2

公开(公告)日：2018-05-22

申请号：US15037755

申请日：2015-09-29

Applicant: Boe Technology Group Co., Ltd.

Inventor： Jian Xu ,  Pan Li ,  Xingchen Shangguan ,  Yong Hu

IPC: G02F1/1362 ,  G02F1/1368 ,  G09G3/36

CPC classification number: G02F1/136204 ,  G02F1/136286 ,  G02F1/1368 ,  G09G3/36 ,  G09G3/3677 ,  G09G2300/0408 ,  G09G2320/0257 ,  G09G2330/027 ,  G09G2330/04

Abstract: The disclosure provides an array substrate and a display device. The array substrate comprises a plurality of gate lines and a gate driving circuit for providing scan signals to the plurality of gate lines successively. The array substrate further comprises a discharge signal line for releasing electric charges and a discharge circuit arranged between the discharge signal line and the plurality of gate lines. The discharge circuit is used for enabling the plurality of gate lines to be electrically connected with the discharge signal line when the gate driving circuit turns off.

公开(公告)号：US09835922B2

公开(公告)日：2017-12-05

申请号：US14771428

申请日：2015-03-27

Applicant: BOE TECHNOLOGY GROUP CO., LTD

Inventor： Hongfei Cheng ,  Jianbo Xian ,  Yong Qiao ,  Yongchun Lu ,  Yongda Ma ,  Jian Xu ,  Wenbo Li ,  Pan Li

IPC: G02F1/1362 ,  G02F1/1343 ,  G02F1/1368 ,  G02F1/1335 ,  H01L27/02 ,  H01L27/12

CPC classification number: G02F1/1368 ,  G02F1/133514 ,  G02F1/134336 ,  G02F1/136213 ,  G02F1/13624 ,  G02F2001/134345 ,  H01L27/0207 ,  H01L27/124 ,  H01L27/1255 ,  H01L27/1259

Abstract: An array substrate and a liquid crystal display device are provided. The array substrate comprises a plurality of columns of pixel units defined by adjacent data lines; each column of pixel units includes a plurality of pixel units, each pixel unit includes a first subpixel electrode, a second subpixel electrode, a first thin film transistor, a second thin film transistor and a third thin film transistor; each pixel unit further includes: a gate line arranged between the first subpixel electrode and the second subpixel electrode; the gate line being electrically connected with a gate electrode of the first thin film transistor, a gate electrode of the second thin film transistor and a gate electrode of the third thin film transistor respectively.

公开(公告)号：US09784997B2

公开(公告)日：2017-10-10

申请号：US15323844

申请日：2015-06-18

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Pan Li ,  Wenbo Li ,  Hongfel Cheng ,  Jianbo Xian

IPC: G02F1/133 ,  G09G3/20 ,  G09G3/36 ,  G02F1/1362 ,  G02F1/1343 ,  G02F1/1368

CPC classification number: G02F1/13306 ,  G02F1/133 ,  G02F1/134336 ,  G02F1/1362 ,  G02F1/13624 ,  G02F1/136286 ,  G02F1/1368 ,  G02F2001/134345 ,  G02F2201/121 ,  G02F2201/123 ,  G09G3/2003 ,  G09G3/3648 ,  G09G3/3677 ,  G09G3/3688 ,  G09G2300/0426 ,  G09G2300/0447 ,  G09G2300/0452 ,  G09G2300/0465 ,  G09G2320/0223 ,  G09G2320/028

Abstract: An array substrate, a display device, and a driving method therefor are provided. The array substrate includes multiple pixel units, multiple scan signal lines (2), and multiple data signal lines (3). The pixel units comprise multiple subpixels (10). The subpixels (10) include first sub-subpixels (101) and second sub-subpixels (102). The multiple data signal lines (3) form multiple data signal line sets. The data signal line sets include multiple data signal line subsets. The data signal line subsets include first data signal lines (Sm+1) and second data signal lines (Sm). The first sub-subpixels (101) are connected to the first data signal lines (Sm+1) to acquire a first data signal. The second sub-subpixels (102) are connected to the second data signal lines (Sm) to acquire a second data signal. The voltage of the first data signal is a V. The value interval for the voltage of the second data signal is (0.7a V, a V)∪(a V, 1.3a V). Using the driving method, the display device is provided with a wide viewing angle.

公开(公告)号：US09704885B2

公开(公告)日：2017-07-11

申请号：US14908236

申请日：2015-04-24

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Pan Li ,  Wenbo Li ,  Yong Qiao ,  Hongfei Cheng ,  Jianbo Xian

IPC: H01L29/10 ,  H01L27/12 ,  G02F1/1368 ,  G02F1/1343 ,  H01L29/417 ,  H01L29/786 ,  G02F1/1337

CPC classification number: H01L27/1222 ,  G02F1/133707 ,  G02F1/134309 ,  G02F1/1368 ,  G02F2001/134345 ,  G02F2201/123 ,  G02F2201/124 ,  G02F2201/40 ,  H01L27/12 ,  H01L29/41733 ,  H01L29/78696

Abstract: A pixel structure, an array substrate and a display device. The pixel substrate comprises a first pixel electrode and a second pixel electrode arranged in a first direction, and a thin film transistor (TFT) disposed between the first pixel electrode and the second pixel electrode. The TFT includes a comb-shaped source, a comb-shaped first drain and a comb-shaped second drain; and a channel region of the TFT is defined by the comb-shaped source respectively and the comb-shaped first drain and the comb-shaped second drain. The channel region has a greater ratio of width to length, thus improving the driving capability of the TFT for driving the first pixel electrode and the second pixel electrode.

公开(公告)号：US20170084668A1

公开(公告)日：2017-03-23

申请号：US15310504

申请日：2016-03-28

Applicant: BOE Technology Group Co., Ltd.

Inventor： Long Wang ,  Libin Liu ,  Pan Li ,  Jiayang Zhao ,  Chun Jan Wang ,  Li Zhou

IPC: H01L27/28 ,  G06F3/041 ,  H01L27/32 ,  G06F3/042

Abstract: An OLED display substrate, a touch display panel and a display device are provided. The OLED display substrate has a base substrate and a display region, the display region includes: a plurality of first sub-regions arranged at intervals and second sub-regions located between the first sub-regions; at least one OLED light-emitting unit located in the first sub-regions; a plurality of optical sensing units located in the second sub-regions, and first drive electrode lines and first transmission electrode lines connected with the optical sensing units and intersecting with each other; wherein, the optical sensing unit includes a photosensitive sensor, and the photosensitive sensor is configured to generate an electric signal according to a light intensity change of a sensed touch point; and the first drive electrode line and the first transmission electrode line are configured to provide the electric signal to determine a position of the touch point.

公开(公告)号：US09557614B2

公开(公告)日：2017-01-31

申请号：US14771748

申请日：2015-04-20

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Hongfei Cheng ,  Jianbo Xian ,  Yong Qiao ,  Yongchun Lu ,  Jian Xu ,  Yongda Ma ,  Wenbo Li ,  Pan Li

IPC: G02F1/1343 ,  G02F1/1362 ,  G02F1/1368

CPC classification number: G02F1/134336 ,  G02F1/133707 ,  G02F1/134309 ,  G02F1/1362 ,  G02F1/136213 ,  G02F1/13624 ,  G02F1/136286 ,  G02F1/1368 ,  G02F2001/134318 ,  G02F2001/134345 ,  G02F2201/121 ,  G02F2201/123

Abstract: A display substrate includes a first base substrate; a gate line, a data line and a common electrode line arranged on the first base substrate; a plurality of pixel units each including a first sub-pixel electrode, a second sub-pixel electrode, a first thin film transistor, a second thin film transistor and a third thin film transistor; and a charge adjustment-control line arranged on the first base substrate, where the charge adjustment-control line and the gate line are between the first sub-pixel electrode and the second sub-pixel electrode. The first thin film transistor is connected to the gate line, the data line and the first sub-pixel electrode; the second thin film transistor is connected to the gate line, the data line and the second sub-pixel electrode; the third thin film transistor is connected to the charge adjustment control line, the first sub-pixel electrode and the common electrode line.

Abstract translation: 显示基板包括：第一基底; 布线在第一基底上的栅极线，数据线和公共电极线; 多个像素单元，每个像素单元包括第一子像素电极，第二子像素电极，第一薄膜晶体管，第二薄膜晶体管和第三薄膜晶体管; 以及电荷调节控制线，其布置在所述第一基底上，所述电荷调节控制线和所述栅极线在所述第一子像素电极和所述第二子像素电极之间。 第一薄膜晶体管连接到栅极线，数据线和第一子像素电极; 第二薄膜晶体管连接到栅极线，数据线和第二子像素电极; 第三薄膜晶体管连接到电荷调节控制线，第一子像素电极和公共电极线。

公开(公告)号：US20160260399A1

公开(公告)日：2016-09-08

申请号：US14893316

申请日：2015-05-21

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Pan Li ,  Wenbo Li ,  Hongfei Cheng ,  Yong Qiao ,  Jianbo Xian

IPC: G09G3/36

CPC classification number: G09G3/3648 ,  G02F1/133707 ,  G02F1/136227 ,  G02F1/136286 ,  G02F1/1368 ,  G02F2001/134345 ,  G09G3/3607 ,  G09G2300/0426 ,  G09G2300/0443 ,  G09G2300/0447 ,  G09G2300/0465 ,  H01L27/1214 ,  H01L27/3248 ,  H01L27/3262 ,  H01L27/3274 ,  H01L29/41733 ,  H01L29/42384 ,  H01L29/4908

Abstract: A pixel structure, an array substrate, a display panel and a display apparatus are disclosed. The pixel structure includes: a first pixel electrode and a second pixel electrode which are arranged along a first direction, and a TFT between the first pixel electrode and the second pixel electrode. The first pixel electrode includes a first extension electrode extending toward the second pixel electrode, and the second pixel electrode includes a second extension electrode extending toward the first pixel electrode; the TFT includes a gate electrode, a source electrode, a first drain electrode and a second drain electrode which are insulated from each other; the source electrode includes a first opening and a second opening, the first drain electrode is connected with the first extension electrode and extends into the first opening, and the second drain electrode is connected with the second extension electrode and extends into the second opening.

Abstract translation: 公开了像素结构，阵列基板，显示面板和显示装置。 像素结构包括：沿着第一方向布置的第一像素电极和第二像素电极，以及在第一像素电极和第二像素电极之间的TFT。 第一像素电极包括朝向第二像素电极延伸的第一延伸电极，第二像素电极包括朝向第一像素电极延伸的第二延伸电极; TFT包括彼此绝缘的栅电极，源电极，第一漏电极和第二漏电极; 源电极包括第一开口和第二开口，第一漏电极与第一延伸电极连接并延伸到第一开口中，第二漏电极与第二延伸电极连接并延伸到第二开口中。