公开(公告)号：US06455432B1

公开(公告)日：2002-09-24

申请号：US09729220

申请日：2000-12-05

申请人： Teng-Chun Tsai ,  Chia-Lin Hsu ,  Yung-Tsung Wei ,  Ming-Sheng Yang

发明人： Teng-Chun Tsai ,  Chia-Lin Hsu ,  Yung-Tsung Wei ,  Ming-Sheng Yang

IPC分类号： H01L21461

CPC分类号： H01L21/7684 ,  H01L21/02074 ,  H01L21/31053 ,  Y10S438/906

摘要： A method for removing carbon-rich particles adhered on a copper surface, especially on a copper surface of a copper/low k dielectric dual damascene structure is provided. A barrier layer and a barrier-CMP stopping layer are formed between the copper layer and the low k dielectric layer of the dual damascene structure. After a Cu-CMP process and a barrier CMP process, a chemical buffing polishing process using an acidic aqueous solution under a downward force of about 0.5 to 3 psi is performed to remove carbon-rich particles adhered on the exposed copper surface, which is due to the low k dielectric layer having at least 90% carbon element being exposed and then polished during the Cu-CMP process and the barrier CMP process, resulting from a dishing phenomenon of the copper layer occurring during the two CMP processes. Alternately, a first chemical buffing polishing process is followed after the Cu-CMP process, and a second chemical buffing polishing process is followed after the barrier CMP process.

摘要翻译： 提供了一种去除附着在铜表面上的富碳颗粒的方法，特别是在铜/低k电介质双镶嵌结构的铜表面上。 在双镶嵌结构的铜层和低k电介质层之间形成阻挡层和阻挡CMP阻挡层。 在Cu-CMP工艺和阻挡CMP工艺之后，进行在约0.5至3psi的向下的力下使用酸性水溶液的化学抛光抛光工艺，以除去粘附在暴露的铜表面上的富碳颗粒，这是由于 到具有至少90％的碳元素的低k电介质层被暴露，然后在Cu-CMP工艺和阻挡CMP工艺期间被抛光，这是由于在两个CMP工艺期间发生的铜层的凹陷现象引起的。 或者，在Cu-CMP工艺之后进行第一次化学抛光抛光工艺，并且在阻挡CMP工艺之后遵循第二次化学抛光抛光工艺。

公开(公告)号：US06403469B1

公开(公告)日：2002-06-11

申请号：US09660071

申请日：2000-09-12

申请人： Teng-Chun Tsai ,  Hsueh-Chung Chen ,  Ming-Sheng Yang

发明人： Teng-Chun Tsai ,  Hsueh-Chung Chen ,  Ming-Sheng Yang

IPC分类号： H01L214763

CPC分类号： H01L21/7684

摘要： A method of producing a dual damascene structure. A substrate is provided and an insulation layer is formed over the substrate. A dual damascene opening is formed in the insulation layer. A liner layer is formed over the exposed surface of the dual damascene opening. Metallic material is deposited over the substrate filling the dual damascene opening to form a metallic layer. A cap layer is formed over the metallic layer. A chemical-mechanical polishing operation is carried out to polish the cap layer using a metal-reactive solution or a cap-layer-reactive solution. The polishing operation continues until the cap layer outside the dual damascene opening is completely removed and the metallic layer is exposed. A portion of the cap layer remains above the dual damascene opening. Using the retained cap layer as a protective layer for the metallic layer, the metallic layer outside the dual damascene opening is removed by polishing until the liner layer is exposed. Lastly, the liner layer is removed to form a slightly protruding metal line structure.

摘要翻译： 一种制造双镶嵌结构的方法。 提供衬底并且在衬底上形成绝缘层。 在绝缘层中形成双镶嵌开口。 在双镶嵌开口的暴露表面上形成衬里层。 金属材料沉积在填充双镶嵌开口的基底上以形成金属层。 在金属层上形成覆盖层。 进行化学机械抛光操作以使用金属反应性溶液或盖层反应性溶液来抛光盖层。 抛光操作继续，直到双镶嵌开口外的盖层被完全去除并且金属层被暴露。 盖层的一部分保留在双镶嵌开口的上方。 使用保留的盖层作为金属层的保护层，通过抛光除去双镶嵌开口外侧的金属层直到衬里层露出。 最后，去除衬里层以形成稍微突出的金属线结构。

公开(公告)号：US06251711B1

公开(公告)日：2001-06-26

申请号：US09531108

申请日：2000-03-17

申请人： Edberg Fang ,  Wen-Yi Hsieh ,  Teng-Chun Tsai

发明人： Edberg Fang ,  Wen-Yi Hsieh ,  Teng-Chun Tsai

IPC分类号： H01L21335

CPC分类号： H01L29/66583 ,  H01L21/28052 ,  H01L21/28518

摘要： The proposed invention is a salicide process that is used to avoid bridge phenomena. In short, the proposed method for forming silicide without bridge phenomena comprises following steps: providing a substrate with a pad layer on the substrate; forming a first cap layer on the pad layer; defining a trench region; removing part of both the pad layer and the first cap layer that are located inside the trench region such that a trench is formed; filling the trench by a gate oxide layer and a polysilicon layer in sequence; capping a first metal layer on the polysilicon layer; performing a first rapid thermal process to form a first silicide layer over the gate oxide layer; removing excess the first metal layer; forming a second cap layer on the first silicide layer; planarizing surface of both the first cap layer and the second cap layer; removing the first cap layer; removing part of the pad layer that is not covered by the gate oxide layer and then a gate structure being formed; forming two light doped drain in the substrate; forming a spacer on sidewall of the gate structure; forming a sources and a drain in the substrate, herein the source and the drain is located around the light doped drains; forming some second metal layers on both the source and the drain; performing a second thermal process to form two second silicide layer over the source and the drain; removing excess the second metal layer; and then forming a third rapid thermal process.

摘要翻译： 所提出的发明是用于避免桥梁现象的自杀过程。 简而言之，所提出的无桥现象形成硅化物的方法包括以下步骤：在衬底上提供衬垫层; 在所述垫层上形成第一盖层; 限定沟槽区域; 去除位于沟槽区域内部的衬垫层和第一覆盖层的部分，使得形成沟槽; 按栅极氧化层和多晶硅层依次填充沟槽; 在多晶硅层上覆盖第一金属层; 执行第一快速热处理以在所述栅极氧化物层上形成第一硅化物层; 去除多余的第一金属层; 在所述第一硅化物层上形成第二盖层; 平坦化第一盖层和第二盖层的表面; 移除所述第一盖层; 去除未被栅极氧化物层覆盖的焊盘层的一部分，然后形成栅极结构; 在衬底中形成两个光掺杂漏极; 在栅极结构的侧壁上形成间隔物; 在衬底中形成源极和漏极，源极和漏极位于光掺杂漏极周围; 在源极和漏极上形成一些第二金属层; 执行第二热处理以在源极和漏极上形成两个第二硅化物层; 去除多余的第二金属层; 然后形成第三快速热处理。

公开(公告)号：US09184100B2

公开(公告)日：2015-11-10

申请号：US13206533

申请日：2011-08-10

申请人： Teng-Chun Tsai ,  Chun-Yuan Wu ,  Chih-Chien Liu ,  Chin-Cheng Chien ,  Chin-Fu Lin

发明人： Teng-Chun Tsai ,  Chun-Yuan Wu ,  Chih-Chien Liu ,  Chin-Cheng Chien ,  Chin-Fu Lin

IPC分类号： H01L27/092 ,  H01L21/84 ,  H01L21/8238 ,  H01L27/12 ,  H01L29/10

CPC分类号： H01L21/845 ,  H01L21/823821 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/1054 ,  H01L29/165

摘要： A semiconductor device includes a semiconductor substrate, at least a first fin structure, at least a second fin structure, a first gate, a second gate, a first source/drain region and a second source/drain region. The semiconductor substrate has at least a first active region to dispose the first fin structure and at least a second active region to dispose the second fin structure. The first/second fin structure partially overlapped by the first/second gate has a first/second stress, and the first stress and the second stress are different from each other. The first/second source/drain region is disposed in the first/second fin structure at two sides of the first/second gate.

摘要翻译： 半导体器件包括半导体衬底，至少第一鳍结构，至少第二鳍结构，第一栅极，第二栅极，第一源极/漏极区域和第二源极/漏极区域。 半导体衬底至少具有第一有源区以配置第一鳍结构和至少第二有源区以配置第二鳍结构。 与第一/第二栅极部分重叠的第一/第二鳍结构具有第一/第二应力，第一应力和第二应力彼此不同。 第一/第二源极/漏极区域设置在第一/第二栅极的两侧的第一/第二鳍结构中。

公开(公告)号：US08828745B2

公开(公告)日：2014-09-09

申请号：US13176790

申请日：2011-07-06

申请人： Wei-Che Tsao ,  Chia-Lin Hsu ,  Jen-Chieh Lin ,  Teng-Chun Tsai ,  Hsin-Kuo Hsu ,  Ya-Hsueh Hsieh ,  Ren-Peng Huang ,  Chih-Hsien Chen ,  Wen-Chin Lin ,  Yung-Lun Hsieh

发明人： Wei-Che Tsao ,  Chia-Lin Hsu ,  Jen-Chieh Lin ,  Teng-Chun Tsai ,  Hsin-Kuo Hsu ,  Ya-Hsueh Hsieh ,  Ren-Peng Huang ,  Chih-Hsien Chen ,  Wen-Chin Lin ,  Yung-Lun Hsieh

IPC分类号： H01L21/66 ,  H01L21/306 ,  H01L21/304 ,  H01L21/768 ,  H01L21/3105 ,  H01L21/321

CPC分类号： H01L21/31053 ,  H01L21/3212 ,  H01L21/76898 ,  H01L22/12 ,  H01L22/26 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for manufacturing TSVs, wherein the method comprises several steps as follows: A stack structure having a substrate and an ILD layer (inter layer dielectric layer) is provided, in which an opening penetrating through the ILD layer and further extending into the substrate is formed. After an insulator layer and a metal barrier layer are formed on the stack structure and the sidewalls of the opening, a top metal layer is then formed on the stack structure to fulfill the opening. A first planarization process stopping on the barrier layer is conducted to remove a portion of the top metal layer. A second planarization process stopping on the ILD layer is subsequently conducted to remove a portion of the metal barrier layer, a portion of the insulator layer and a portion of the top metal layer, wherein the second planarization process has a polishing endpoint determined by a light interferometry or a motor current.

摘要翻译： 一种制造TSV的方法，其中该方法包括以下几个步骤：提供具有基板和ILD层（层间电介质层）的堆叠结构，其中穿透ILD层并进一步延伸到基板中的开口是 形成。 在堆叠结构和开口的侧壁上形成绝缘体层和金属阻挡层之后，在堆叠结构上形成顶部金属层以实现开口。 进行停止在阻挡层上的第一平面化处理以去除顶部金属层的一部分。 随后进行停止在ILD层上的第二平坦化处理以去除金属阻挡层的一部分，绝缘体层的一部分和顶部金属层的一部分，其中第二平坦化工艺具有由光线确定的抛光终点 干涉测量或电机电流。

公开(公告)号：US08822336B2

公开(公告)日：2014-09-02

申请号：US13161849

申请日：2011-06-16

申请人： Teng-Chun Tsai ,  Chun-Yuan Wu ,  Chin-Fu Lin ,  Chih-Chien Liu ,  Chin-Cheng Chien

发明人： Teng-Chun Tsai ,  Chun-Yuan Wu ,  Chin-Fu Lin ,  Chih-Chien Liu ,  Chin-Cheng Chien

IPC分类号： H01L21/283

CPC分类号： H01L21/76898 ,  H01L21/76883

摘要： A through-silicon via forming method includes the following steps. Firstly, a semiconductor substrate is provided. Then, a through-silicon via conductor is formed in the semiconductor substrate, and a topside of the through-silicon via conductor is allowed to be at the same level as a surface of the semiconductor substrate. Afterwards, a portion of the through-silicon via conductor is removed, and the topside of the through-silicon via conductor is allowed to be at a level lower than the surface of the semiconductor substrate, so that a recess is formed over the through-silicon via conductor.

摘要翻译： 通硅通孔形成方法包括以下步骤。 首先，提供半导体衬底。 然后，在半导体衬底中形成贯通硅通孔导体，并且使贯通硅通孔导体的上侧与半导体衬底的表面处于相同的水平。 然后，去除一部分通硅导通导体，使贯通硅通孔导体的顶面位于比半导体衬底的表面低的水平面上， 硅通孔导体。

公开(公告)号：US08779526B2

公开(公告)日：2014-07-15

申请号：US13283603

申请日：2011-10-28

申请人： Chun-Wei Hsu ,  Po-Cheng Huang ,  Ren-Peng Huang ,  Jie-Ning Yang ,  Chia-Lin Hsu ,  Teng-Chun Tsai ,  Chih-Hsun Lin ,  Chang-Hung Kung ,  Yen-Ming Chen ,  Yu-Ting Li

发明人： Chun-Wei Hsu ,  Po-Cheng Huang ,  Ren-Peng Huang ,  Jie-Ning Yang ,  Chia-Lin Hsu ,  Teng-Chun Tsai ,  Chih-Hsun Lin ,  Chang-Hung Kung ,  Yen-Ming Chen ,  Yu-Ting Li

IPC分类号： H01L29/78

CPC分类号： H01L27/0629

摘要： A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a transistor region and a resistor region; forming a shallow trench isolation (STI) on the substrate of the resistor region; forming a tank in the STI of the resistor region; and forming a resistor in the tank and on the surface of the STI adjacent to two sides of the tank.

摘要翻译： 公开了半导体器件的制造方法。 该方法包括以下步骤：提供具有晶体管区域和电阻器区域的衬底; 在电阻器区域的衬底上形成浅沟槽隔离（STI）; 在电阻区域的STI中形成槽; 并且在罐中形成电阻器，并且在与槽的两侧相邻的STI的表面上形成电阻器。

公开(公告)号：US08513128B2

公开(公告)日：2013-08-20

申请号：US13162776

申请日：2011-06-17

申请人： Chun-Wei Hsu ,  Po-Cheng Huang ,  Teng-Chun Tsai ,  Chia-Lin Hsu ,  Chih-Hsun Lin ,  Chang-Hung Kung ,  Chia-His Chen ,  Yen-Ming Chen

发明人： Chun-Wei Hsu ,  Po-Cheng Huang ,  Teng-Chun Tsai ,  Chia-Lin Hsu ,  Chih-Hsun Lin ,  Chang-Hung Kung ,  Chia-His Chen ,  Yen-Ming Chen

IPC分类号： H01L21/304 ,  H01L21/306 ,  B44C1/22

CPC分类号： H01L21/31053 ,  H01L21/02065 ,  H01L29/517 ,  H01L29/66545

摘要： A poly opening polish process includes the following steps. A semi-finished semiconductor component is provided. The semi-finished semiconductor component includes a substrate, a gate disposed on the substrate, and a dielectric layer disposed on the substrate and covering the gate. A first polishing process is applied onto the dielectric layer. A second polishing process is applied to the gate. The second polishing process utilizes a wetting solution including a water soluble polymer surfactant, an alkaline compound and water. The poly opening polish process can effectively remove an oxide residue formed in the chemical mechanical polish, thereby improving the performance of the integrated circuit and reducing the production cost of the integrated circuit.

摘要翻译： 多孔抛光工艺包括以下步骤。 提供半成品半导体元件。 半成品半导体部件包括基板，设置在基板上的栅极和设置在基板上并覆盖栅极的电介质层。 将第一抛光工艺施加到电介质层上。 第二次抛光工艺应用于浇口。 第二抛光工艺利用包含水溶性聚合物表面活性剂，碱性化合物和水的润湿溶液。 多孔抛光工艺可有效去除化学机械抛光中形成的氧化物残留物，从而提高集成电路的性能，降低集成电路的生产成本。

公开(公告)号：US20130078778A1

公开(公告)日：2013-03-28

申请号：US13243485

申请日：2011-09-23

申请人： Chin-Cheng Chien ,  Chun-Yuan Wu ,  Chih-Chien Liu ,  Chin-Fu Lin ,  Teng-Chun Tsai

发明人： Chin-Cheng Chien ,  Chun-Yuan Wu ,  Chih-Chien Liu ,  Chin-Fu Lin ,  Teng-Chun Tsai

IPC分类号： H01L21/336

CPC分类号： H01L29/66795

摘要： A semiconductor process is described as follows. A plurality of dummy patterns is formed on a substrate. A mask material layer is conformally formed on the substrate, so as to cover the dummy patterns. The mask material layer has an etching rate different from that of the dummy patterns. A portion of the mask material layer is removed, so as to form a mask layer on respective sidewalls of each dummy pattern. An upper surface of the mask layer and an upper surface of each dummy pattern are substantially coplanar. The dummy patterns are removed. A portion of the substrate is removed using the mask layer as a mask, so as to form a plurality of fin structures and a plurality of trenches alternately arranged in the substrate. The mask layer is removed.

摘要翻译： 半导体工艺描述如下。 在基板上形成多个虚设图案。 在基板上共形形成掩模材料层，以覆盖虚设图案。 掩模材料层具有与虚拟图案不同的蚀刻速率。 除去掩模材料层的一部分，以便在每个虚设图案的各个侧壁上形成掩模层。 掩模层的上表面和每个虚拟图案的上表面基本上共面。 虚拟图案被去除。 使用掩模层作为掩模去除衬底的一部分，以便形成多个翅片结构和交替布置在衬底中的多个沟槽。 去除掩模层。

公开(公告)号：US20130056827A1

公开(公告)日：2013-03-07

申请号：US13224344

申请日：2011-09-02

申请人： Shih-Hung Tsai ,  Chien-Ting Lin ,  Chin-Cheng Chien ,  Chin-Fu Lin ,  Chih-Chien Liu ,  Teng-Chun Tsai ,  Chun-Yuan Wu

发明人： Shih-Hung Tsai ,  Chien-Ting Lin ,  Chin-Cheng Chien ,  Chin-Fu Lin ,  Chih-Chien Liu ,  Teng-Chun Tsai ,  Chun-Yuan Wu

IPC分类号： H01L21/84 ,  H01L27/12 ,  H01L21/336 ,  H01L29/78

CPC分类号： H01L29/785 ,  H01L29/66795

摘要： A non-planar semiconductor structure includes a substrate, at least two fin-shaped structures, at least an isolation structure, and a plurality of epitaxial layers. The fin-shaped structures are located on the substrate. The isolation structure is located between the fin-shaped structures, and the isolation structure has a nitrogen-containing layer. The epitaxial layers respectively cover a part of the fin-shaped structures and are located on the nitrogen-containing layer. A non-planar semiconductor process is also provided for forming the semiconductor structure.

摘要翻译： 非平面半导体结构包括衬底，至少两个鳍状结构，至少一个隔离结构和多个外延层。 鳍状结构位于基底上。 隔离结构位于鳍状结构之间，隔离结构具有含氮层。 外延层分别覆盖了鳍状结构的一部分并且位于含氮层上。 还提供了用于形成半导体结构的非平面半导体工艺。