Process for spin-on coating with an organic material having a low dielectric constant
    51.
    发明授权
    Process for spin-on coating with an organic material having a low dielectric constant 失效
    用具有低介电常数的有机材料进行旋涂的方法

    公开(公告)号:US06365228B1

    公开(公告)日:2002-04-02

    申请号:US09685430

    申请日:2000-10-10

    Abstract: A process for spin-on coating with an organic material having a low dielectric constant, which is suitable for a substrate. A dielectric base layer capable of protecting metal is formed on the substrate, an adhesive promoter layer is formed on the dielectric base layer, and the adhesive promoter layer is baked. A solvent is then used to clean the substrate and simultaneously to dissolve a part of the adhesive promoter layer in order to flatten the adhesive promoter layer. Afterwards, a layer of an organic material with a low dielectric constant is spin-on coated on the adhesive promoter layer, and the layer of an organic material with a low dielectric constant is baked and cured.

    Abstract translation: 一种适用于基材的具有低介电常数的有机材料的旋涂方法。 在基板上形成能够保护金属的电介质基层,在电介质基底层上形成粘合剂促进剂层,并烘烤粘合促进剂层。 然后使用溶剂来清洁基底并同时溶解部分粘合促进剂层以使粘合剂促进剂层变平。 然后,将具有低介电常数的有机材料层旋涂在粘合剂促进剂层上,并且将具有低介电常数的有机材料层烘焙和固化。

    Method of forming a dual damascene with dummy metal lines
    52.
    发明授权
    Method of forming a dual damascene with dummy metal lines 有权
    用虚拟金属线形成双镶嵌的方法

    公开(公告)号:US6001733A

    公开(公告)日:1999-12-14

    申请号:US164856

    申请日:1998-10-01

    Abstract: A method for forming dual damascene is provided. First, a first inter-metal dielectric layer and a stop layer is formed on a substrate, and then a first photoresist pattern including a via hole and a dummy metal line is patterned and the stop layer is etched for forming via hole. Next, a second inter-metal dielectric layer is deposited and then a second photoresist pattern is patterned for forming metal line trench by etching. Afterwards, a glue layer and a metal layer are blanketed and the dual damascene structure is formed by chemical mechanical polishing.

    Abstract translation: 提供了一种形成双镶嵌的方法。 首先,在基板上形成第一金属间介电层和停止层,然后对包括通孔和虚拟金属线的第一光致抗蚀剂图案进行图案化,并且对停止层进行蚀刻以形成通孔。 接下来,沉积第二金属间介电层,然后对第二光致抗蚀剂图案进行图案化以通过蚀刻形成金属线沟槽。 然后,胶合层和金属层被覆盖,并通过化学机械抛光形成双镶嵌结构。

    Liner for a cargo container
    53.
    发明授权
    Liner for a cargo container 失效
    货物集装箱的内衬

    公开(公告)号:US5487485A

    公开(公告)日:1996-01-30

    申请号:US421535

    申请日:1995-04-13

    CPC classification number: B65D90/048 B65D2590/046

    Abstract: A liner for a cargo container includes an expansible liner body shaped to fit a cargo space of the cargo container. The liner body includes top and bottom panels, left and right panels interconnecting the top and bottom panels, and front and rear panels. The top, bottom, left, right, front and rear panels together define an accommodation space thereamong for receiving bulk cargo. The rear panel has an outlet opening communicated with the accommodation space. Two first and second reinforcing members are secured respectively to and along the front edges of the left and right panels. Two first and second connecting members are secured respectively to and along the left and right edges of the bottom panel near the rear panel. Two left and right pulling members are mounted respectively to the first and second connecting members to pull the first and second connecting members upwardly and to raise the dead corners formed adjacent to the first and second connecting members to cause parts of the bulk cargo retaining in the dead corners to fall towards the outlet opening.

    Abstract translation: 用于货物集装箱的衬里包括形状适合货物集装箱的货物空间的可膨胀衬管主体。 衬套主体包括顶部和底部面板,互连顶部和底部面板以及前后面板的左右面板。 顶部,底部,左侧,右侧,前部和后部面板一起定义了用于接收散装货物的容纳空间。 后面板具有与容纳空间连通的出口。 两个第一加强件和第二加强件分别固定在左边板和右边板的前边缘上。 两个第一和第二连接构件分别固定在底板的左右边缘并靠近后面板。 两个左右牵引构件分别安装在第一和第二连接构件上以将第一和第二连接构件向上拉动并且使靠近第一和第二连接构件形成的死角升高,以使散装货物的一部分保持在 死角落到出口处。

    Semiconductor Device
    54.
    发明申请
    Semiconductor Device 审中-公开
    半导体器件

    公开(公告)号:US20140264913A1

    公开(公告)日:2014-09-18

    申请号:US13833464

    申请日:2013-03-15

    CPC classification number: H01L23/481 H01L23/528 H01L2924/0002 H01L2924/00

    Abstract: A semiconductor device comprises a substrate, a through-silicon via (TSV) penetrating the substrate, at least one first interconnect structure traversing the TSV from the top and dividing a region right above the TSV into several sub-regions and being configured for interconnect routing of an active device and a plurality of second interconnect structures occupying the sub-regions right above the TSV and being configured for electrically coupling the TSV to a higher-level interconnect.

    Abstract translation: 半导体器件包括衬底,穿透衬底的穿硅通孔(TSV),从顶部穿过TSV的至少一个第一互连结构,并将TSV正上方的区域划分成若干子区域并被配置用于互连路由 有源器件和多个第二互连结构占据TSV正上方的子区域并且被配置为将TSV电耦合到较高级互连。

    Method for fabricating an image sensor device
    55.
    发明授权
    Method for fabricating an image sensor device 有权
    图像传感器装置的制造方法

    公开(公告)号:US08283110B2

    公开(公告)日:2012-10-09

    申请号:US12816743

    申请日:2010-06-16

    CPC classification number: H01L27/14685 H01L27/14627 H01L27/14698

    Abstract: A method for fabricating an image sensor device is disclosed. The method for fabricating an image sensor device comprises forming a photosensitive layer on a substrate. The photosensitive layer is exposed through a first photomask to form an exposed portion and an unexposed portion. The unexposed portion is partially exposed through a second photomask to form a trimmed part, wherein the second photomask comprise a first segment and a second segment that has a transmittance greater than that of the first segment. The trimmed part is removed to form photosensitive structures. The photosensitive structures are reflowed to form a first microlens and a second microlens having different heights.

    Abstract translation: 公开了一种用于制造图像传感器装置的方法。 图像传感器装置的制造方法包括在基板上形成感光层。 感光层通过第一光掩模曝光以形成曝光部分和未曝光部分。 未曝光部分通过第二光掩模部分曝光以形成修剪部分,其中第二光掩模包括第一光栅和第二光栅,其具有大于第一光栅的透射率。 去除修剪的部分以形成光敏结构。 光敏结构被回流以形成具有不同高度的第一微透镜和第二微透镜。

    METHOD FOR FABRICATING AN IMAGE SENSOR DEVICE
    56.
    发明申请
    METHOD FOR FABRICATING AN IMAGE SENSOR DEVICE 有权
    用于制作图像传感器装置的方法

    公开(公告)号:US20110311919A1

    公开(公告)日:2011-12-22

    申请号:US12816743

    申请日:2010-06-16

    CPC classification number: H01L27/14685 H01L27/14627 H01L27/14698

    Abstract: A method for fabricating an image sensor device is disclosed. The method for fabricating an image sensor device comprises forming a photosensitive layer on a substrate. The photosensitive layer is exposed through a first photomask to form an exposed portion and an unexposed portion. The unexposed portion is partially exposed through a second photomask to form a trimmed part, wherein the second photomask comprise a first segment and a second segment that has a transmittance greater than that of the first segment. The trimmed part is removed to form photosensitive structures. The photosensitive structures are reflowed to form a first microlens and a second microlens having different heights.

    Abstract translation: 公开了一种用于制造图像传感器装置的方法。 图像传感器装置的制造方法包括在基板上形成感光层。 感光层通过第一光掩模曝光以形成曝光部分和未曝光部分。 未曝光部分通过第二光掩模部分曝光以形成修剪部分,其中第二光掩模包括第一光栅和第二光栅,其具有大于第一光栅的透射率。 去除修剪的部分以形成光敏结构。 光敏结构被回流以形成具有不同高度的第一微透镜和第二微透镜。

    AIR GAP FOR TUNGSTEN/ALUMINUM PLUG APPLICATIONS
    57.
    发明申请
    AIR GAP FOR TUNGSTEN/ALUMINUM PLUG APPLICATIONS 审中-公开
    用于TUNGSTEN /铝插头应用的空气隙

    公开(公告)号:US20070076339A1

    公开(公告)日:2007-04-05

    申请号:US11561790

    申请日:2006-11-20

    CPC classification number: H01L21/7682 H01L21/76807

    Abstract: An air gap structure substantially reduces undesired capacitance between adjacent interconnects, metal lines or other features in an integrated circuit device. The air gap extends above, and may also additionally extend below, the interconnects desired to be isolated thus minimizing fringing fields between the lines. The integrated air gap structure can be utilized in conjunction with a tungsten plug process. Also, multiple levels of the integrated air gap structure can be fabricated to accommodate multiple metal levels while always ensuring that physical dielectric layer support is provided to the device structure underlying the interconnects.

    Abstract translation: 气隙结构基本上减少了集成电路器件中相邻互连,金属线或其他特征之间的不需要的电容。 空气间隙在期望被隔离的互连之上延伸并且还可以另外延伸,从而最小化线之间的边缘场。 集成气隙结构可以与钨丝塞过程一起使用。 此外,可以制造多个级别的集成气隙结构以适应多个金属水平,同时始终确保将物理介电层支撑件提供给互连下面的器件结构。

    Chemical mechanical polishing in forming semiconductor device
    58.
    发明授权
    Chemical mechanical polishing in forming semiconductor device 有权
    化学机械抛光成型半导体器件

    公开(公告)号:US06790742B2

    公开(公告)日:2004-09-14

    申请号:US10293243

    申请日:2002-11-13

    CPC classification number: H01L21/76229

    Abstract: A method of chemical-mechanical polishing for forming a shallow trench isolation is disclosed. A substrate having a number of active regions, including a number of relatively large active regions and a number of relative small active regions, is provided. The method comprises the following steps. A silicon nitride layer on the substrate is formed. A number of shallow trenches are formed between the active regions one or more of which may constitute an alignment mark. An oxide layer is formed over the substrate, so that the shallow trenches are filled with the oxide layer. A partial reverse active mask is formed on the oxide layer. The partial reverse active mask exposes a portion of the oxide layer over the large active area and over the alignment mark. The oxide layer of each large active region and the alignment mark is removed. The partial reverse active mask is removed. The oxide layer is planarized.

    Abstract translation: 公开了用于形成浅沟槽隔离的化学机械抛光的方法。 提供了具有多个有效区域的基板,包括多个相对较大的有源区域和多个相对小的有源区域。 该方法包括以下步骤。 形成衬底上的氮化硅层。 在有源区域之间形成多个浅沟槽,其中一个或多个可以构成对准标记。 在衬底上形成氧化物层,使得浅沟槽被氧化物层填充。 在氧化物层上形成部分反向有源掩模。 部分反向有源掩模将氧化物层的一部分暴露在大的有效区域上方和对准标记之上。 去除每个大活性区域的氧化物层和对准标记。 去除部分反向主动掩模。 氧化层平坦化。

    Chemical mechanical polishing method for copper

    公开(公告)号:US06616510B2

    公开(公告)日:2003-09-09

    申请号:US09735323

    申请日:2000-12-12

    CPC classification number: H01L21/3212 B24B37/044 C09G1/02

    Abstract: A chemical-mechanical polishing method for polishing a copper oxide layer and a copper layer. The copper oxide layer above the copper layer is first polished using an aqueous solution having a high concentration of polishing particles/chelating agent. The copper layer is then polished using a polishing slurry having a low concentration of polishing particles/chelating agent or the polishing slurry free of polishing particles/chelating agent. Alternatively, the copper oxide layer is polished using a mixture of the aqueous solution and the polishing slurry. After the copper oxide layer is removed, the copper layer is polished using the polishing slurry alone.

    Method of forming dual damascene structure
    60.
    发明授权
    Method of forming dual damascene structure 有权
    形成双镶嵌结构的方法

    公开(公告)号:US06440861B1

    公开(公告)日:2002-08-27

    申请号:US09652471

    申请日:2000-08-31

    CPC classification number: H01L21/76835 H01L21/76808 H01L2221/1063

    Abstract: A method of forming a dual damascene structure. A first dielectric layer and a second dielectric layer are sequentially formed over a substrate. A first photoresist layer is formed over the second dielectric layer. Photolithographic and etching operations are conducted to remove a portion of the second dielectric layer and the first dielectric layer so that a via opening is formed. A conformal third dielectric layer is coated over the surface of the second dielectric layer and the interior surface of the via opening. The conformal third dielectric layer forms a liner dielectric layer. A second photoresist layer is formed over the second dielectric layer and then the second photoresist layer is patterned. Using the patterned second photoresist layer as a mask, a portion of the second dielectric layer is removed to form a trench. The patterned second photoresist layer is removed. Conductive material is deposited over the substrate to fill the via opening and the trench. Finally, chemical-mechanical polishing is conducted to remove excess conductive material above the second dielectric layer.

    Abstract translation: 形成双镶嵌结构的方法。 第一电介质层和第二电介质层依次形成在衬底上。 在第二介电层上形成第一光致抗蚀剂层。 进行光刻和蚀刻操作以去除第二介电层和第一介电层的一部分,从而形成通孔。 保形第三电介质层涂覆在第二电介质层的表面和通孔开口的内表面上。 保形第三电介质层形成衬里电介质层。 在第二电介质层上形成第二光致抗蚀剂层,然后对第二光致抗蚀剂层进行图案化。 使用图案化的第二光致抗蚀剂层作为掩模,去除第二介电层的一部分以形成沟槽。 去除图案化的第二光致抗蚀剂层。 导电材料沉积在衬底上以填充通孔和沟槽。 最后,进行化学机械抛光以除去第二介电层上方的多余的导电材料。

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