公开(公告)号：US06406959B2

公开(公告)日：2002-06-18

申请号：US09225893

申请日：1999-01-04

Applicant: Kirk D. Prall ,  Gregg Rettschlag ,  Graham Wolstenholme

Inventor： Kirk D. Prall ,  Gregg Rettschlag ,  Graham Wolstenholme

IPC: H01L218247

CPC classification number: H01L27/11521 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/11 ,  H01L27/1116 ,  H01L27/11546

Abstract: In one implementation, a method of forming an array of FLASH memory includes forming a plurality of lines of floating gates extending from a memory array area to a peripheral circuitry area over a semiconductor substrate. In a common masking step, discrete openings are formed over a) at least some of the lines of floating gates in the peripheral circuitry area, and b) floating gate source area in multiple lines along at least portions of the lines of floating gates within the memory array area. In one implementation, a line of floating gates is formed over a semiconductor substrate. A conductive line different from the line of floating gates is formed over the semiconductor substrate. In a common masking step, discrete openings are formed to a) at least one of the conductive line and the line of floating gates, and b) floating gate source area of multiple transistors comprising the line of floating gates along at least a portion of the line of floating gates. In one implementation, a method of forming FLASH memory and SRAM circuitry includes forming a line of floating gates over a semiconductor substrate and an SRAM gate over the semiconductor substrate. In a common masking step, discrete openings are formed over a) the SRAM gate, and b) floating gate source area of multiple transistors comprising the line of floating gates along at least a portion of the line of floating gates. Other implementations are disclosed.

Abstract translation: 在一个实施方式中，形成闪存阵列的方法包括形成多个从存储器阵列区域延伸到半导体衬底上的外围电路区域的浮动栅极线。 在通常的屏蔽步骤中，在a）外围电路区域中的浮动栅极的至少一些行上形成离散的开口，以及b）沿着浮动栅极的线的至少部分的多条线中的浮动栅极源极区域 存储器阵列区域。 在一个实施方案中，在半导体衬底上形成一行浮栅。 在半导体衬底上形成与浮栅的线不同的导线。 在通常的掩蔽步骤中，形成离散开口以a）至少一个导电线和浮置栅极线，以及b）多个晶体管的浮置栅极源区，其包括沿着至少一部分 一排浮动门。 在一个实施方式中，形成FLASH存储器和SRAM电路的方法包括在半导体衬底上半导体衬底和SRAM栅极上形成一行浮动栅极。 在常见的屏蔽步骤中，在SRAM栅极上形成离散的开口，以及b）沿着浮动栅极线的至少一部分的包括浮置栅极线的多个晶体管的浮动栅极源极区域。 公开了其他实现。

公开(公告)号：US06333556B1

公开(公告)日：2001-12-25

申请号：US08947847

申请日：1997-10-09

Applicant: Werner Juengling ,  Kirk D. Prall ,  Ravi Iyer ,  Gurtej S. Sandhu ,  Guy Blalock

Inventor： Werner Juengling ,  Kirk D. Prall ,  Ravi Iyer ,  Gurtej S. Sandhu ,  Guy Blalock

IPC: H01L23485

CPC classification number: H01L21/7682 ,  H01L21/02115 ,  H01L21/02118 ,  H01L21/02167 ,  H01L21/02203 ,  H01L21/02274 ,  H01L21/02282 ,  H01L21/02362 ,  H01L21/31695 ,  H01L21/76826 ,  H01L21/76828 ,  H01L21/76829 ,  H01L21/76834 ,  H01L23/5222 ,  H01L23/5329 ,  H01L2221/1047 ,  H01L2924/0002 ,  Y10T428/12014 ,  Y10T428/24149 ,  Y10T428/249921 ,  Y10T428/25 ,  Y10T428/259 ,  H01L2924/00

Abstract: The invention encompasses methods of forming insulating materials between conductive elements. In one aspect, the invention includes a method of forming a material adjacent a conductive electrical component comprising: a) partially vaporizing a mass to form a matrix adjacent the conductive electrical component, the matrix having at least one void within it. In another aspect, the invention includes a method of forming a material between a pair of conductive electrical components comprising the following steps: a) forming a pair of conductive electrical components within a mass and separated by an expanse of the mass; b) forming at least one support member within the expanse of the mass, the support member not comprising a conductive interconnect; and c) vaporizing the expanse of the mass to a degree effective to form at least one void between the support member and each of the pair of conductive electrical components. In another aspect, the invention includes an insulating material adjacent a conductive electrical component, the insulating material comprising a matrix and at least one void within the matrix. In another aspect, the invention includes an insulating region between a pair of conductive electrical components comprising: a) a support member between the conductive electrical components, the support member not comprising a conductive interconnect; and b) at least one void between the support member and each of the pair of conductive electrical components.

Abstract translation: 本发明包括在导电元件之间形成绝缘材料的方法。 在一个方面，本发明包括形成邻近导电电气部件的材料的方法，该方法包括：a）部分蒸发物质以形成邻近导电电气部件的基体，所述基质在其内具有至少一个空隙。 另一方面，本发明包括一种在一对导电电气部件之间形成材料的方法，包括以下步骤：a）在质量体内形成一对导电的电气部件，并由质量块的一部分分隔; b）在所述物体的宽度内形成至少一个支撑构件，所述支撑构件不包括导电互连; 以及c）将所述物质的所述膨胀物蒸发至有效地在所述支撑构件和所述一对导电电气部件中的每一个之间形成至少一个空隙的程度。 在另一方面，本发明包括与导电电气部件相邻的绝缘材料，所述绝缘材料包含基体和所述基体内的至少一个空隙。 在另一方面，本发明包括在一对导电电气部件之间的绝缘区域，包括：a）导电电气部件之间的支撑部件，所述支撑部件不包括导电互连; 以及b）所述支撑构件和所述一对导电电气部件中的每一个之间的至少一个空隙。

公开(公告)号：US06313046B1

公开(公告)日：2001-11-06

申请号：US09115339

申请日：1998-07-14

Applicant: Werner Juengling ,  Kirk D. Prall ,  Ravi Iyer ,  Gurtej S. Sandhu ,  Guy Blalock

Inventor： Werner Juengling ,  Kirk D. Prall ,  Ravi Iyer ,  Gurtej S. Sandhu ,  Guy Blalock

IPC: H01L2131

CPC classification number: H01L21/7682 ,  H01L21/02115 ,  H01L21/02118 ,  H01L21/02167 ,  H01L21/02203 ,  H01L21/02274 ,  H01L21/02282 ,  H01L21/02362 ,  H01L21/31695 ,  H01L21/76826 ,  H01L21/76828 ,  H01L21/76829 ,  H01L21/76834 ,  H01L23/5222 ,  H01L23/5329 ,  H01L2221/1047 ,  H01L2924/0002 ,  Y10T428/12014 ,  Y10T428/24149 ,  Y10T428/249921 ,  Y10T428/25 ,  Y10T428/259 ,  H01L2924/00

Abstract: The invention encompasses methods of forming insulating materials between conductive elements. In one aspect, the invention includes a method of forming a material adjacent a conductive electrical component comprising: a) partially vaporizing a mass to form a matrix adjacent the conductive electrical component, the matrix having at least one void within it. In another aspect, the invention includes a method of forming a material between a pair of conductive electrical components comprising the following steps: a) forming a pair of conductive electrical components within a mass and separated by an expanse of the mass; b) forming at least one support member within the expanse of the mass, the support member not comprising a conductive interconnect; and c) vaporizing the expanse of the mass to a degree effective to form at least one void between the support member and each of the pair of conductive electrical components. In another aspect, the invention includes an insulating material adjacent a conductive electrical component, the insulating material comprising a matrix and at least one void within the matrix. In another aspect, the invention includes an insulating region between a pair of conductive electrical components comprising: a) a support member between the conductive electrical components, the support member not comprising a conductive interconnect; and b) at least one void between the support member and each of the pair of conductive electrical components.

Abstract translation: 本发明涵盖在导电元件之间形成绝缘材料的方法。 在一个方面，本发明包括形成邻近导电电气部件的材料的方法，该方法包括：a）部分蒸发物质以形成邻近导电电气部件的基体，所述基质在其内具有至少一个空隙。 另一方面，本发明包括一种在一对导电电气部件之间形成材料的方法，包括以下步骤：a）在质量体内形成一对导电的电气部件，并由质量块的一部分分隔; b）在所述物体的宽度内形成至少一个支撑构件，所述支撑构件不包括导电互连; 以及c）将所述物质的所述膨胀物蒸发至有效地在所述支撑构件和所述一对导电电气部件中的每一个之间形成至少一个空隙的程度。 在另一方面，本发明包括与导电电气部件相邻的绝缘材料，所述绝缘材料包含基体和所述基体内的至少一个空隙。 在另一方面，本发明包括在一对导电电气部件之间的绝缘区域，包括：a）导电电气部件之间的支撑部件，所述支撑部件不包括导电互连; 以及b）所述支撑构件和所述一对导电电气部件中的每一个之间的至少一个空隙。

公开(公告)号：US06166426A

公开(公告)日：2000-12-26

申请号：US233871

申请日：1999-01-20

Applicant: Kirk D. Prall ,  Mike P. Violette

Inventor： Kirk D. Prall ,  Mike P. Violette

IPC: H01L21/331 ,  H01L21/8222 ,  H01L21/8249 ,  H01L27/06 ,  H01L27/082 ,  H01L29/735 ,  H01L27/102 ,  H01L29/70 ,  H01L31/11

CPC classification number: H01L29/6625 ,  H01L21/8222 ,  H01L21/8249 ,  H01L27/0623 ,  H01L27/082 ,  H01L29/735

Abstract: A substantially concentric lateral bipolar transistor and the method of forming same. A base region is disposed about a periphery of an emitter region, and a collector region is disposed about a periphery of the base region to form the concentric lateral bipolar transistor of the invention. A gate overlies the substrate and at least a portion of the base region. At least one electrical contact is formed connecting the base and the gate, although a plurality of contacts may be formed. A further bipolar transistor is formed according to the following method of the invention. A base region is formed in a substrate and a gate region is formed overlying at least a portion of the base region. Emitter and collector terminals are formed on opposed sides of the base region. The gage is used as a mask during first and second ion implants. During the first ion implant the ions bombard the substrate from a first direction to grade a base/emitter junction, and during the second ion implant ions bombard the substrate from a second direction to grade a base/collector junction. Also a lateral bipolar transistor having a decreased base width as a result of implanting ions after fabrication of collector and emitter regions to enlarge the collector and emitter regions, thereby decreasing the base region and increasing gain.

Abstract translation: 基本同心的横向双极晶体管及其形成方法。 基极区域围绕发射极区域的周边设置，并且集电极区域围绕基极区域的周边设置以形成本发明的同心横向双极晶体管。 栅极覆盖衬底和基极区域的至少一部分。 形成连接基座和栅极的至少一个电触头，尽管可以形成多个触点。 根据本发明的以下方法形成另外的双极晶体管。 在基板中形成基极区域，并且形成覆盖基极区域的至少一部分的栅极区域。 发射极和集电极端子形成在基极区域的相对侧上。 在第一和第二离子植入物期间，将量规用作掩模。 在第一离子注入期间，离子从第一方向轰击衬底以分级基极/发射极结，并且在第二离子注入期间，离子从第二方向轰击衬底以对基极/集电极结进行分级。 另外，作为在集电极和发射极区域制造之后注入离子的结果，具有减小的基极宽度的横向双极晶体管，以扩大集电极和发射极区域，从而减小基极区域并增加增益。

公开(公告)号：US5986347A

公开(公告)日：1999-11-16

申请号：US107930

申请日：1998-06-30

Applicant: Kevin G. Donohoe ,  Kirk D. Prall

Inventor： Kevin G. Donohoe ,  Kirk D. Prall

IPC: H01L21/311 ,  H01L21/768 ,  H01L23/48 ,  H01L29/46

CPC classification number: H01L21/31116 ,  H01L21/76804

Abstract: Methods of forming contact openings over a node location and related integrated circuitry are described. In one aspect of the invention, a node location is formed within a semiconductive substrate adjacent an isolation oxide region. A layer of material is formed over the node location and a contact opening is etched through the layer of material to outwardly expose a node location planar upper surface. In one preferred implementation, the contact opening includes an inner surface portion which faces generally transversely away from the isolation oxide region and which defines an angle with the node location upper surface which is greater at a bottom of the contact opening than at a top of the contact opening. In another preferred implementation, the contact opening includes sidewall portions which define a profile which having a non-uniform degree of taper between the contact opening top and bottom. In another preferred implementation, the tapering of the contact opening is effectuated by modifying at least one etching parameter at an intermediate etching point and continuing the etching to outwardly expose the node location.

Abstract translation: 描述了在节点位置和相关集成电路上形成接触开口的方法。 在本发明的一个方面，节点位置形成在与隔离氧化物区域相邻的半导体衬底内。 在节点位置上形成一层材料，并且通过该材料层蚀刻一个接触开口以向外暴露节点位置平坦的上表面。 在一个优选实施例中，接触开口包括内表面部分，其大体上横向远离隔离氧化物区域并且与节点位置上表面形成一角度，其在接触开口的底部比在顶部处 接触开口 在另一个优选的实施方式中，接触开口包括限定轮廓的侧壁部分，该轮廓在接触开口顶部和底部之间具有不均匀的锥度。 在另一优选实施例中，通过在中间蚀刻点处修改至少一个蚀刻参数并且继续蚀刻以向外暴露节点位置来实现接触开口的渐缩。

公开(公告)号：US5866453A

公开(公告)日：1999-02-02

申请号：US527924

申请日：1995-09-14

Applicant: Kirk D. Prall ,  Pierre Fazan ,  Trung Doan ,  Tyler Lowrey

Inventor： Kirk D. Prall ,  Pierre Fazan ,  Trung Doan ,  Tyler Lowrey

IPC: H01L21/8242 ,  H01L27/108 ,  H01L21/20

CPC classification number: H01L27/10852 ,  H01L27/10808

Abstract: An etch process for increasing the alignment tolerances between capacitor components and an adjacent contact corridor in Dynamic Random Access Memories. The etch process is implemented in a capacitor structure formed over a semiconductor substrate. The capacitor structure includes a first conductor, a dielectric layer on the first conductor and a second conductor on the dielectric layer. The second conductor has a horizontal region laterally adjacent to and extending away from the first conductor. The etch process comprises the steps of: (a) forming a layer of patterned photoresist over the second conductor, the photoresist being patterned to expose a portion of the horizontal region of the second conductor at a desired location of a contact corridor above a source/drain region in the substrate; (b) using the photoresist as an etch mask, anisotropically etching away the exposed portions of the horizontal region of the second conductor; and (c) using the photoresist again as an etch mask, isotropically etching away substantially all of the remaining portions of the horizontal region of the second conductor and thereby enlarging the area available for locating the contact corridor. Alternatively, the horizontal region of the second conductor is removed using a single isotropic etch.

Abstract translation: 用于增加动态随机存取存储器中电容器组件与相邻触点走廊之间的对准公差的蚀刻工艺。 蚀刻工艺在半导体衬底上形成的电容器结构中实现。 电容器结构包括第一导体，第一导体上的电介质层和电介质层上的第二导体。 第二导体具有横向邻近并远离第一导体延伸的水平区域。 蚀刻工艺包括以下步骤：（a）在第二导体上形成图案化光致抗蚀剂层，光刻胶被图案化以在第二导体的水平区域的一个源/ 漏极区域; （b）使用光致抗蚀剂作为蚀刻掩模，各向异性地蚀刻掉第二导体的水平区域的暴露部分; 和（c）再次使用光致抗蚀剂作为蚀刻掩模，各向同性地蚀刻掉第二导体的水平区域的基本上所有其余部分，从而扩大可用于定位接触走廊的面积。 或者，使用单个各向同性蚀刻去除第二导体的水平区域。

公开(公告)号：US5341016A

公开(公告)日：1994-08-23

申请号：US78700

申请日：1993-06-16

Applicant: Kirk D. Prall ,  Gurtej S. Sandhu ,  Scott G. Meikle

Inventor： Kirk D. Prall ,  Gurtej S. Sandhu ,  Scott G. Meikle

IPC: H01L21/28 ,  H01L21/336 ,  H01L23/532 ,  H01L27/02

CPC classification number: H01L29/66575 ,  H01L21/28088 ,  H01L23/53257 ,  H01L2924/0002 ,  Y10S257/915

Abstract: A composite semiconductor structure which replaces polysilicon for conductive device elements and provides lower resistance interconnections between devices. The preferred structure is a conductive adhesion layer deposited in place of polysilicon in contact with a conductive metal layer traversing the interconnection. The preferred material for the adhesion layer is tungsten nitride, and for the metal layer--tungsten. If polysilicon is retained for device elements, the adhesion and metal layers may be placed in contact with the polysilicon element and along the interconnect structure providing an interconnect with lower resistance. Increased adhesion may be obtained by adding a cap layer of dielectric material atop the metal layer.

Abstract translation: 一种复合半导体结构，其替代用于导电器件元件的多晶硅并且在器件之间提供较低的电阻互连。 优选的结构是代替与穿过互连的导电金属层接触的多晶硅沉积的导电粘合层。 用于粘合层的优选材料是氮化钨，对于金属层钨。 如果多晶硅被保留用于器件元件，则粘附和金属层可以放置成与多晶硅元件接触并沿着互连结构提供具有较低电阻的互连。 可以通过在金属层顶部添加电介质材料的覆盖层来获得增加的附着力。

公开(公告)号：US09287275B2

公开(公告)日：2016-03-15

申请号：US12544773

申请日：2009-08-20

Applicant: Gurtej S. Sandhu ,  Kirk D. Prall

Inventor： Gurtej S. Sandhu ,  Kirk D. Prall

IPC: H01L29/76 ,  H01L27/115 ,  H01L21/28

CPC classification number: H01L27/115 ,  H01L21/28273 ,  H01L27/11521

Abstract: Some embodiments include methods of forming flash memory cells and semiconductor constructions, and some embodiments include semiconductor constructions. Some embodiments may include a method in which a semiconductor substrate is provided to have a plurality of active area locations. Floating gates are formed over the active area locations, with the floating gates having widths that are entirely sub-lithographic. Adjacent floating gates are spaced from one another by gaps. Dielectric material and control gate material are formed over the floating gates and within the gaps. Some embodiments may include a construction in which a pair of adjacent floating gates are over a pair of adjacent active areas, with the floating gates being spaced from one another by a distance which is greater than a distance that the active areas are spaced from one another.

Abstract translation: 一些实施例包括形成快闪存储器单元和半导体结构的方法，并且一些实施例包括半导体结构。 一些实施例可以包括其中提供半导体衬底以具有多个有效区域位置的方法。 浮动栅极形成在有源区位置上，浮栅具有完全亚光刻的宽度。 相邻的浮动门通过间隙彼此间隔开。 电介质材料和控制栅极材料形成在浮动栅极和间隙内。 一些实施例可以包括其中一对相邻浮动栅极在一对相邻有效区域之上的结构，其中浮动栅极彼此间隔一定距离，该距离大于有效区域彼此间隔开的距离 。

公开(公告)号：US08841645B2

公开(公告)日：2014-09-23

申请号：US13618860

申请日：2012-09-14

Applicant: Durai Vishak Nirmal Ramaswamy ,  Kirk D. Prall

Inventor： Durai Vishak Nirmal Ramaswamy ,  Kirk D. Prall

IPC: H01L45/00 ,  G11C11/00

CPC classification number: H01L45/04 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/146 ,  H01L45/147

Abstract: Some embodiments include a memory device and methods of forming the same. The memory device can include an electrode coupled to a memory element. The electrode can include different materials located at different portions of the electrode. The materials can create different dielectrics contacting the memory elements at different locations. Various states of the materials in the memory device can be used to represent stored information. Other embodiments are described.

Abstract translation: 一些实施例包括存储器件及其形成方法。 存储器件可以包括耦合到存储元件的电极。 电极可以包括位于电极的不同部分的不同材料。 这些材料可以在不同位置产生接触存储元件的不同电介质。 可以使用存储器件中的材料的各种状态来表示存储的信息。 描述其他实施例。

公开(公告)号：US08681529B2

公开(公告)日：2014-03-25

申请号：US13293353

申请日：2011-11-10

Applicant: Zengtao T. Liu ,  Kirk D. Prall ,  Mike Violette

Inventor： Zengtao T. Liu ,  Kirk D. Prall ,  Mike Violette

IPC: G11C11/00

CPC classification number: H01L27/2436 ,  G11C5/063 ,  G11C8/14 ,  G11C11/56 ,  G11C13/0002 ,  G11C13/0021 ,  G11C13/003 ,  G11C13/004 ,  G11C13/0069 ,  G11C2213/74 ,  G11C2213/78 ,  G11C2213/79 ,  H01L27/222 ,  H01L27/228 ,  H01L27/24 ,  H01L27/2463 ,  H01L43/08 ,  H01L43/10 ,  H01L45/065 ,  H01L45/085 ,  H01L45/141 ,  H01L45/146 ,  H01L45/147

Abstract: Methods and apparatuses that include resistive memory can include a first memory cell coupled to a data line and including a first resistive storage element and a first access device, a second memory cell coupled to the data line and including a second resistive storage element and a second access device, an isolation device formed between the first access device and the second access device, a first select line coupled to the first resistive storage element, and a second select line coupled to the second resistive storage element, wherein the second select line is separate from the first select line.

Abstract translation: 包括电阻性存储器的方法和装置可以包括耦合到数据线并包括第一电阻存储元件和第一存取器件的第一存储器单元，耦合到数据线的第二存储单元，并且包括第二电阻存储元件和第二存储单元 接入设备，形成在第一接入设备和第二接入设备之间的隔离设备，耦合到第一电阻存储元件的第一选择线以及耦合到第二电阻存储元件的第二选择线，其中第二选择线是分开的 从第一选择行。