公开(公告)号：US06406959B2

公开(公告)日：2002-06-18

申请号：US09225893

申请日：1999-01-04

Applicant: Kirk D. Prall ,  Gregg Rettschlag ,  Graham Wolstenholme

Inventor： Kirk D. Prall ,  Gregg Rettschlag ,  Graham Wolstenholme

IPC: H01L218247

CPC classification number: H01L27/11521 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/11 ,  H01L27/1116 ,  H01L27/11546

Abstract: In one implementation, a method of forming an array of FLASH memory includes forming a plurality of lines of floating gates extending from a memory array area to a peripheral circuitry area over a semiconductor substrate. In a common masking step, discrete openings are formed over a) at least some of the lines of floating gates in the peripheral circuitry area, and b) floating gate source area in multiple lines along at least portions of the lines of floating gates within the memory array area. In one implementation, a line of floating gates is formed over a semiconductor substrate. A conductive line different from the line of floating gates is formed over the semiconductor substrate. In a common masking step, discrete openings are formed to a) at least one of the conductive line and the line of floating gates, and b) floating gate source area of multiple transistors comprising the line of floating gates along at least a portion of the line of floating gates. In one implementation, a method of forming FLASH memory and SRAM circuitry includes forming a line of floating gates over a semiconductor substrate and an SRAM gate over the semiconductor substrate. In a common masking step, discrete openings are formed over a) the SRAM gate, and b) floating gate source area of multiple transistors comprising the line of floating gates along at least a portion of the line of floating gates. Other implementations are disclosed.

Abstract translation: 在一个实施方式中，形成闪存阵列的方法包括形成多个从存储器阵列区域延伸到半导体衬底上的外围电路区域的浮动栅极线。 在通常的屏蔽步骤中，在a）外围电路区域中的浮动栅极的至少一些行上形成离散的开口，以及b）沿着浮动栅极的线的至少部分的多条线中的浮动栅极源极区域 存储器阵列区域。 在一个实施方案中，在半导体衬底上形成一行浮栅。 在半导体衬底上形成与浮栅的线不同的导线。 在通常的掩蔽步骤中，形成离散开口以a）至少一个导电线和浮置栅极线，以及b）多个晶体管的浮置栅极源区，其包括沿着至少一部分 一排浮动门。 在一个实施方式中，形成FLASH存储器和SRAM电路的方法包括在半导体衬底上半导体衬底和SRAM栅极上形成一行浮动栅极。 在常见的屏蔽步骤中，在SRAM栅极上形成离散的开口，以及b）沿着浮动栅极线的至少一部分的包括浮置栅极线的多个晶体管的浮动栅极源极区域。 公开了其他实现。

公开(公告)号：US20090072347A1

公开(公告)日：2009-03-19

申请号：US12276235

申请日：2008-11-21

Applicant: Michael A. Smith ,  Sukesh Sandhu ,  Xianfeng Zhou ,  Graham Wolstenholme

Inventor： Michael A. Smith ,  Sukesh Sandhu ,  Xianfeng Zhou ,  Graham Wolstenholme

IPC: H01L29/06

CPC classification number: H01L29/7833 ,  H01L21/76205

Abstract: The invention includes methods of forming oxide structures under corners of transistor gate stacks and adjacent trenched isolation regions. Such methods can include exposure of a semiconductor material to steam and H2, with the H2 being present to a concentration of from about 2% to about 40%, by volume. An oxide structure formed under the bottom corner of a transistor gate stack can have a bottom surface with a topography that includes a step of at least about 50 Å, and an upper surface directly over the bottom surface and having a topography that is substantially planar. Methodology of the present invention can be utilized to form semiconductor constructions suitable for incorporation into highly integrated circuitry. The highly integrated circuitry can be incorporated into electronic systems, and can, for example, be utilized in processors and/or memory storage devices.

Abstract translation: 本发明包括在晶体管栅极堆叠和相邻沟槽隔离区域的角落处形成氧化物结构的方法。 这样的方法可以包括将半导体材料暴露于蒸汽和H2，其中H2以体积计约2％至约40％的浓度存在。 形成在晶体管栅极堆叠的底角下方的氧化物结构可以具有底表面，其具有包括至少约为50埃的步骤的形貌，以及直接在底表面上方的上表面，并且具有基本平坦的形貌。 本发明的方法可以用于形成适合并入高度集成电路的半导体结构。 高度集成的电路可以并入到电子系统中，并且可以例如在处理器和/或存储器存储设备中使用。

公开(公告)号：US07473615B2

公开(公告)日：2009-01-06

申请号：US11197882

申请日：2005-08-05

Applicant: Michael A. Smith ,  Sukesh Sandhu ,  Xianfeng Zhou ,  Graham Wolstenholme

Inventor： Michael A. Smith ,  Sukesh Sandhu ,  Xianfeng Zhou ,  Graham Wolstenholme

IPC: H01L21/76

CPC classification number: H01L29/7833 ,  H01L21/76205

Abstract: The invention includes methods of forming oxide structures under corners of transistor gate stacks and adjacent trenched isolation regions. Such methods can include exposure of a semiconductor material to steam and H2, with the H2 being present to a concentration of from about 2% to about 40%, by volume. An oxide structure formed under the bottom corner of a transistor gate stack can have a bottom surface with a topography that includes a step of at least about 50 Å, and an upper surface directly over the bottom surface and having a topography that is substantially planar. Methodology of the present invention can be utilized to form semiconductor constructions suitable for incorporation into highly integrated circuitry. The highly integrated circuitry can be incorporated into electronic systems, and can, for example, be utilized in processors and/or memory storage devices.

Abstract translation: 本发明包括在晶体管栅极堆叠和相邻沟槽隔离区域的角落处形成氧化物结构的方法。 这样的方法可以包括将半导体材料暴露于蒸汽和H2，其中H2以体积计约2％至约40％的浓度存在。 形成在晶体管栅极堆叠的底角下方的氧化物结构可以具有底表面，其具有包括至少约为50埃的步骤的形貌，以及直接在底表面上方的上表面，并且具有基本平坦的形貌。 本发明的方法可以用于形成适合并入高度集成电路的半导体结构。 高度集成的电路可以并入到电子系统中，并且可以例如在处理器和/或存储器存储设备中使用。

公开(公告)号：US20060019449A1

公开(公告)日：2006-01-26

申请号：US11233569

申请日：2005-09-23

Applicant: Graham Wolstenholme ,  Mark Helm

Inventor： Graham Wolstenholme ,  Mark Helm

IPC: H01L21/8234

CPC classification number: H01L27/10894 ,  H01L21/76224 ,  H01L21/823462 ,  H01L21/823481 ,  H01L21/823857 ,  H01L21/823878 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/10897 ,  Y10S438/981 ,  Y10T29/41 ,  Y10T29/5313

Abstract: A dielectric layer (e.g., an interpoly dielectric layer) is deposited over low and high voltage devices of a peripheral memory device. The dielectric behaves as an oxidation and wet oxide etch barrier. The dielectric prevents the devices from being stripped by a wet oxide etch that can result in the exposure of the silicon corners. The exposure of a silicon corner may increase thinning of a gate oxide at the field edge. This causes variability and unreliability in the device. The dielectric is not removed from a device until the device is ready for processing. That is, the dielectric remains on a device until the growing of a gate oxide on that device has begun. This reduces the exposure of the silicon corner. Hedges that result may be removed by exposing a trench in the field oxide at the hedge.

公开(公告)号：US20060008987A1

公开(公告)日：2006-01-12

申请号：US11217624

申请日：2005-09-01

Applicant: Chun Chen ,  Guy Blalock ,  Graham Wolstenholme ,  Kirk Prall

Inventor： Chun Chen ,  Guy Blalock ,  Graham Wolstenholme ,  Kirk Prall

IPC: H01L21/336 ,  H01L21/44

CPC classification number: H01L27/11521 ,  H01L21/76895 ,  H01L27/115

Abstract: Methods and apparatus are described to facilitate forming memory devices with low resistance polysilicon local interconnects that allow a smaller array feature size and therefore facilitate forming arrays of a denser array format. Embodiments of the present invention are formed utilizing a wet etch process that has a high selectivity, allowing the deposition and etching of polysilicon local interconnects to source regions of array transistors. By providing for a local interconnect of polysilicon, a smaller source region and/or drain region can also be utilized, further decreasing the required word line spacing. Low resistance polysilicon local source interconnects can also couple to an increased number of memory cells, thereby reducing the number of contacts made to an array ground.

公开(公告)号：US20050104114A1

公开(公告)日：2005-05-19

申请号：US10714752

申请日：2003-11-17

Applicant: Chun Chen ,  Guy Blalock ,  Graham Wolstenholme ,  Kirk Prall

Inventor： Chun Chen ,  Guy Blalock ,  Graham Wolstenholme ,  Kirk Prall

IPC: H01L21/336 ,  H01L21/768 ,  H01L21/8247 ,  H01L23/48 ,  H01L27/115 ,  H01L29/76 ,  H01L29/788

CPC classification number: H01L27/11521 ,  H01L21/76895 ,  H01L27/115

Abstract: Methods and apparatus are described to facilitate forming memory devices with low resistance polysilicon local interconnects that allow a smaller array feature size and therefore facilitate forming arrays of a denser array format. Embodiments of the present invention are formed utilizing a wet etch process that has a high selectivity, allowing the deposition and etching of polysilicon local interconnects to source regions of array transistors. By providing for a local interconnect of polysilicon, a smaller source region and/or drain region can also be utilized, further decreasing the required word line spacing. Low resistance polysilicon local source interconnects can also couple to an increased number of memory cells, thereby reducing the number of contacts made to an array ground.

Abstract translation: 描述了方法和装置以便于形成具有低电阻多晶硅局部互连的存储器件，其允许更小的阵列特征尺寸，并因此促进形成更密集阵列格式的阵列。 使用具有高选择性的湿蚀刻工艺形成本发明的实施例，允许将多晶硅局部互连件沉积和蚀刻到阵列晶体管的源极区域。 通过提供多晶硅的局部互连，还可以利用更小的源极区和/或漏极区，进一步减少所需的字线间隔。 低电阻多晶硅本地源极互连还可以耦合到增加数量的存储器单元，从而减少对阵列地阵进行的触点的数量。

公开(公告)号：US06713346B2

公开(公告)日：2004-03-30

申请号：US09768878

申请日：2001-01-23

Applicant: Graham Wolstenholme

Inventor： Graham Wolstenholme

IPC: H01L218247

CPC classification number: H01L27/11521 ,  H01L27/115

Abstract: The invention comprises FLASH memory and methods of forming flash memory. In one implementation, a line of floating gates is formed over a semiconductor substrate. The semiconductor substrate is etched to form a series of spaced trenches therein in a line adjacent and along at least a portion of the line of floating gates. At least one conductivity enhancing impurity implant is conducted into the semiconductor substrate at an angle away from normal to a general orientation of the semiconductor substrate to implant at least along sidewalls of the trenches and between the trenches, and a continuous line of source active area is formed within the semiconductor substrate along at least a portion of the line of floating gates. In another implementation, a line of floating gates is formed over a semiconductor substrate. An alternating series of trench isolation regions and active area regions are provided in the semiconductor substrate in a line adjacent and along at least a portion of the line of floating gates. The series of active areas define discrete transistor source areas separated by trench isolation regions. A conductive line is formed over the discrete transistor source areas and trench isolation regions separating same adjacent and along at least a portion of the line of floating gates. The conductive line electrically interconnects the discrete transistor source areas. Source forming conductivity enhancing impurity is provided into the discrete transistor source areas. Other implementations are contemplated.

Abstract translation: 本发明包括闪速存储器和形成闪速存储器的方法。 在一个实施方案中，在半导体衬底上形成一行浮栅。 蚀刻半导体衬底以在与浮动栅极线的至少一部分相邻并沿其中的线中在其中形成一系列间隔的沟槽。 将至少一种导电性增强杂质注入物以远离法向半导体衬底的大体取向的角度被导入半导体衬底中，至少沿着沟槽的侧壁和沟槽之间注入，并且源有源区的连续线是 沿着所述浮动栅极线的至少一部分在所述半导体衬底内形成。 在另一实施方案中，在半导体衬底上形成一行浮栅。 交替的沟槽隔离区域和有源区域区域被设置在半导体衬底中的与浮动栅极线的至少一部分相邻并且沿着该行的至少一部分的直线中。 一系列有源区域定义了由沟槽隔离区域分离的分立晶体管源极区域。 在离散晶体管源极区域和沟槽隔离区域上形成导线，所述沟槽隔离区域相邻并且沿着浮动栅极线的至少一部分分开相同。 导线将离散晶体管源极区域电连接。 将源极形成导电性增强杂质提供到分立晶体管源极区域中。 考虑其他实现。

公开(公告)号：US08508999B2

公开(公告)日：2013-08-13

申请号：US13451656

申请日：2012-04-20

Applicant: Zengtao Liu ,  Graham Wolstenholme

Inventor： Zengtao Liu ,  Graham Wolstenholme

IPC: G11C11/34

CPC classification number: G11C16/0483 ,  G11C16/16 ,  G11C16/26 ,  H01L27/11521 ,  H01L27/11556 ,  H01L27/11568 ,  H01L27/11582

Abstract: A vertical NAND structure includes one or more mid-string devices having at least two functional modes. In the first mode, the one or more mid-string devices couple the bodies of stacks of NAND memory cells to the substrate for erase operations. In the second mode, the one or more mid-string devices couple the body of a first stack of NAND memory cells to a body of a second stack of memory NAND memory cells, allowing the two stacks operate as a single NAND string for read and programming operations.

Abstract translation: 垂直NAND结构包括具有至少两个功能模式的一个或多个中串式装置。 在第一模式中，一个或多个中串式装置将NAND存储器单元堆叠的主体耦合到衬底以进行擦除操作。 在第二模式中，一个或多个中串装置将第一堆NAND存储器单元的主体耦合到第二堆存储器NAND存储器单元的主体，允许两个堆作为单个NAND串用于读取和 编程操作。

公开(公告)号：US20100276781A1

公开(公告)日：2010-11-04

申请号：US12837378

申请日：2010-07-15

Applicant: Michael A. Smith ,  Sukesh Sandhu ,  Xianfeng Zhou ,  Graham Wolstenholme

Inventor： Michael A. Smith ,  Sukesh Sandhu ,  Xianfeng Zhou ,  Graham Wolstenholme

IPC: H01L29/06

CPC classification number: H01L29/7833 ,  H01L21/76205

Abstract: The invention includes methods of forming oxide structures under corners of transistor gate stacks and adjacent trenched isolation regions. Such methods can include exposure of a semiconductor material to steam and H2, with the H2 being present to a concentration of from about 2% to about 40%, by volume. An oxide structure formed under the bottom corner of a transistor gate stack can have a bottom surface with a topography that includes a step of at least about 50 Å, and an upper surface directly over the bottom surface and having a topography that is substantially planar. Methodology of the present invention can be utilized to form semiconductor constructions suitable for incorporation into highly integrated circuitry. The highly integrated circuitry can be incorporated into electronic systems, and can, for example, be utilized in processors and/or memory storage devices.

Abstract translation: 本发明包括在晶体管栅极堆叠和相邻沟槽隔离区域的角落处形成氧化物结构的方法。 这样的方法可以包括将半导体材料暴露于蒸汽和H2，其中H2以体积计约2％至约40％的浓度存在。 形成在晶体管栅极堆叠的底角下方的氧化物结构可以具有底表面，其具有包括至少约为50埃的步骤的形貌，以及直接在底表面上方的上表面，并且具有基本平坦的形貌。 本发明的方法可以用于形成适合并入高度集成电路的半导体结构。 高度集成的电路可以并入到电子系统中，并且可以例如在处理器和/或存储器存储设备中使用。

公开(公告)号：US20070264784A1

公开(公告)日：2007-11-15

申请号：US11880003

申请日：2007-07-18

Applicant: Graham Wolstenholme ,  Mark Helm

Inventor： Graham Wolstenholme ,  Mark Helm

IPC: H01L21/8234

CPC classification number: H01L27/10894 ,  H01L21/76224 ,  H01L21/823462 ,  H01L21/823481 ,  H01L21/823857 ,  H01L21/823878 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/10897 ,  Y10S438/981 ,  Y10T29/41 ,  Y10T29/5313

Abstract: A dielectric layer (e.g., an interpoly dielectric layer) is deposited over low and high voltage devices of a peripheral memory device. The dielectric behaves as an oxidation and wet oxide etch barrier. The dielectric prevents the devices from being stripped by a wet oxide etch that can result in the exposure of the silicon corners. The exposure of a silicon corner may increase thinning of a gate oxide at the field edge. This causes variability and unreliability in the device. The dielectric is not removed from a device until the device is ready for processing. That is, the dielectric remains on a device until the growing of a gate oxide on that device has begun. This reduces the exposure of the silicon corner. Hedges that result may be removed by exposing a trench in the field oxide at the hedge.