公开(公告)号：US20090267211A1

公开(公告)日：2009-10-29

申请号：US12498913

申请日：2009-07-07

Applicant: Hyun-Soo CHUNG ,  In-Young LEE ,  Son-Kwan HWANG ,  Dong-Ho LEE ,  Seong-Deok HWANG

Inventor： Hyun-Soo CHUNG ,  In-Young LEE ,  Son-Kwan HWANG ,  Dong-Ho LEE ,  Seong-Deok HWANG

IPC: H01L23/52 ,  H01L23/538 ,  H01L23/48

CPC classification number: H01L25/50 ,  H01L21/76898 ,  H01L25/0657 ,  H01L29/0657 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/05567 ,  H01L2224/0557 ,  H01L2224/06181 ,  H01L2224/13025 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06555 ,  H01L2225/06586 ,  H01L2924/0002 ,  H01L2924/01006 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01038 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01093 ,  H01L2224/11 ,  H01L2224/05552

Abstract: Wafer level packages and methods of fabricating the same are provided. In one embodiment, one of the methods comprises forming semiconductor chips having a connection pad on a wafer, patterning a bottom surface of the wafer to form a trench under the connection pad, patterning a bottom surface of the trench to form a via hole exposing the bottom surface of the connection pad, and forming a connecting device connected to the connection pad through the via hole. The invention provides a wafer level package having reduced thickness, lower fabrication costs, and increased reliability compared to conventional packages.

Abstract translation: 提供了晶片级封装及其制造方法。 在一个实施例中，方法之一包括形成在晶片上具有连接焊盘的半导体芯片，图案化晶片的底表面以在连接焊盘下方形成沟槽，图案化沟槽的底表面以形成通孔， 并且通过通孔形成连接到连接垫的连接装置。 本发明提供了与传统封装相比，具有减小的厚度，较低的制造成本和增加的可靠性的晶片级封装。

公开(公告)号：US07545027B2

公开(公告)日：2009-06-09

申请号：US11448772

申请日：2006-06-08

Applicant: Hyun-Soo Chung ,  In-Young Lee ,  Dong-Hyeon Jang ,  Myeong-Soon Park ,  Dong-Ho Lee

Inventor： Hyun-Soo Chung ,  In-Young Lee ,  Dong-Hyeon Jang ,  Myeong-Soon Park ,  Dong-Ho Lee

IPC: H01L23/02

CPC classification number: H01L23/3114 ,  H01L23/525 ,  H01L24/02 ,  H01L24/11 ,  H01L24/12 ,  H01L2224/0231 ,  H01L2224/02311 ,  H01L2224/02313 ,  H01L2224/0401 ,  H01L2224/10126 ,  H01L2224/1191 ,  H01L2224/13022 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/3025

Abstract: A wafer level package may include a semiconductor substrate supporting an electrode pad. A first insulating layer may be provided on the semiconductor substrate. The first insulating layer may include a first opening through which the electrode pad may be exposed. A seed metal layer may be provided on an entire surface of the first insulating layer. A redistribution interconnection metal layer may be provided on the seed metal layer. A second insulating layer may be provided on the redistribution interconnection metal layer. The second insulating layer may have a second opening spaced from the first opening to expose a portion of the redistribution interconnection metal layer. The second insulating layer may surround the redistribution interconnection metal layer. An unwanted portion of seed metal layer may be removed using the second insulating layer as an etch mask.

Abstract translation: 晶片级封装可以包括支撑电极焊盘的半导体衬底。 第一绝缘层可以设置在半导体衬底上。 第一绝缘层可以包括第一开口，电极焊盘可以暴露在第一开口中。 种子金属层可以设置在第一绝缘层的整个表面上。 再分布互连金属层可以设置在种子金属层上。 第二绝缘层可以设置在再分布互连金属层上。 第二绝缘层可以具有与第一开口间隔开的第二开口，以暴露再分布互连金属层的一部分。 第二绝缘层可以包围再分布互连金属层。 可以使用第二绝缘层作为蚀刻掩模去除种子金属层的不需要的部分。

公开(公告)号：US20080128905A1

公开(公告)日：2008-06-05

申请号：US11950251

申请日：2007-12-04

Applicant: In-Young LEE ,  Dong-Ho LEE ,  Nam-Seog KIM ,  Hyun-Soo CHUNG ,  Ho-Jin LEE ,  Myeong-Soo PARK

Inventor： In-Young LEE ,  Dong-Ho LEE ,  Nam-Seog KIM ,  Hyun-Soo CHUNG ,  Ho-Jin LEE ,  Myeong-Soo PARK

IPC: H01L23/488 ,  H01L21/44

CPC classification number: H01L23/525 ,  H01L23/3114 ,  H01L24/11 ,  H01L24/12 ,  H01L24/16 ,  H01L2224/05001 ,  H01L2224/05008 ,  H01L2224/05026 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05548 ,  H01L2224/05569 ,  H01L2224/056 ,  H01L2224/05647 ,  H01L2224/05666 ,  H01L2224/11334 ,  H01L2224/1147 ,  H01L2224/13099 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/351 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/013

Abstract: Provided are a wafer level chip scale package in which a redistribution process is applied at a wafer level, a manufacturing method thereof, and a semiconductor chip module including the wafer level chip scale package. The wafer level chip scale package includes a semiconductor chip having a bonding pad, a first insulating layer disposed on the semiconductor chip so as to expose the bonding pad, a redistribution line disposed on the exposed bonding pad and the first insulating layer, a sacrificial layer disposed below a redistribution pad of the redistribution line, a second insulating layer disposed on the redistribution line so as to expose the redistribution pad and including a crack inducement hole disposed beside the sacrificial layer, and an external connection terminal attached to the redistribution pad.

Abstract translation: 提供了其中在晶片级应用再分配处理的晶片级芯片级封装，其制造方法以及包括晶片级芯片级封装的半导体芯片模块。 晶片级芯片级封装包括具有接合焊盘的半导体芯片，设置在半导体芯片上以暴露焊盘的第一绝缘层，设置在暴露的焊盘和第一绝缘层上的再分配线，牺牲层 设置在所述再分配线的再分配衬垫的下方，设置在所述再分配线上的第二绝缘层，以暴露所述再分配衬垫并且包括设置在所述牺牲层旁边的裂纹诱导孔，以及附接到所述再分布衬垫的外部连接端子。

公开(公告)号：US07307342B2

公开(公告)日：2007-12-11

申请号：US11195361

申请日：2005-08-01

Applicant: Se-Young Jeong ,  Sung-Min Sim ,  Soon-Bum Kim ,  In-Young Lee ,  Young-Hee Song

Inventor： Se-Young Jeong ,  Sung-Min Sim ,  Soon-Bum Kim ,  In-Young Lee ,  Young-Hee Song

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC classification number: H01L24/05 ,  H01L23/3192 ,  H01L24/03 ,  H01L24/11 ,  H01L24/12 ,  H01L2224/0401 ,  H01L2224/05008 ,  H01L2224/05018 ,  H01L2224/05556 ,  H01L2224/05558 ,  H01L2224/05571 ,  H01L2224/05572 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2224/16 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/05042 ,  H01L2924/14 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2224/05552

Abstract: An interconnection structure includes an integrated circuit (IC) chip having internal circuitry and a terminal to electrically connect the internal circuitry to an external circuit, a passivation layer disposed on a top surface of the IC chip, the passivation layer configured to protect the internal circuitry and to expose the terminal, an input/output (I/O) pad, where the I/O pad includes a first portion in contact with the terminal and a second portion that extends over the passivation layer, and an electroless plating layer disposed on the I/O pad.

Abstract translation: 互连结构包括具有内部电路的集成电路（IC）芯片和用于将内部电路电连接到外部电路的端子，设置在IC芯片的顶表面上的钝化层，钝化层被配置为保护内部电路 以及使所述终端暴露于所述I / O焊盘包括与所述端子接触的第一部分和在所述钝化层上延伸的第二部分的输入/输出（I / O）焊盘，以及设置在所述钝化层上的无电镀层 I / O板。

公开(公告)号：US07271084B2

公开(公告)日：2007-09-18

申请号：US11330107

申请日：2006-01-12

Applicant: Se-young Jeong ,  Nam-seog Kim ,  Oh-se Yong ,  Soon-bum Kim ,  Sun-young Park ,  Ju-hyun Lyu ,  In-young Lee

Inventor： Se-young Jeong ,  Nam-seog Kim ,  Oh-se Yong ,  Soon-bum Kim ,  Sun-young Park ,  Ju-hyun Lyu ,  In-young Lee

IPC: H01L21/44 ,  H01L21/461 ,  B23K31/02

CPC classification number: H01L24/13 ,  B23K3/0607 ,  B23K3/0623 ,  H01L21/2885 ,  H01L21/4853 ,  H01L23/49811 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/0401 ,  H01L2224/05599 ,  H01L2224/1147 ,  H01L2224/11901 ,  H01L2224/13012 ,  H01L2224/13076 ,  H01L2224/13078 ,  H01L2224/13099 ,  H01L2224/13111 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/136 ,  H01L2224/16 ,  H01L2224/1601 ,  H01L2224/81141 ,  H01L2224/81143 ,  H01L2224/81193 ,  H01L2224/8121 ,  H01L2224/81815 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01068 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/14 ,  H05K1/111 ,  H05K3/243 ,  H05K3/3436 ,  H05K3/4007 ,  H05K2201/0367 ,  H05K2201/0373 ,  H05K2201/09745 ,  H05K2201/10674 ,  H05K2203/048 ,  H05K2203/167 ,  Y02P70/611 ,  Y02P70/613 ,  H01L2924/00

Abstract: A reinforced solder bump connector structure is formed between a contact pad arranged on a semiconductor chip and a ball pad arranged on a mounting substrate. The semiconductor chip includes at least one reinforcing protrusion extending upwardly from a surface of an intermediate layer. The mounting substrate includes at least one reinforcing protrusion extending upwardly from a ball pad, the protrusions from both the chip and the substrate being embedded within the solder bump connector. In some configurations, the reinforcing protrusions from the contact pad and the ball pad are sized and arranged to have overlapping upper portions. These overlapping portions may assume a wide variety of configurations that allow the protrusions to overlap without contacting each other including pin arrays and combinations of surrounding and surrounded elements. In each configuration, the reinforcing protrusions will tend to suppress crack formation and/or crack propagation thereby improving reliability.

Abstract translation: 在布置在半导体芯片上的接触焊盘和布置在安装基板上的球垫之间形成加强焊料凸块连接器结构。 半导体芯片包括从中间层的表面向上延伸的至少一个增强突起。 安装基板包括从球垫向上延伸的至少一个加强突起，来自芯片和基板的突起被嵌入在焊料凸块连接器内。 在一些构造中，来自接触垫和球垫的加强突起的尺寸和布置为具有重叠的上部。 这些重叠部分可采取各种各样的构造，其允许突起重叠而不彼此接触，包括针阵列以及周围和被包围的元件的组合。 在每种构造中，加强突起将倾向于抑制裂纹形成和/或裂纹扩展，从而提高可靠性。

公开(公告)号：US20070176290A1

公开(公告)日：2007-08-02

申请号：US11717691

申请日：2007-03-14

Applicant: Myeong-Soon Park ,  Hyun-Soo Chung ,  In-Young Lee ,  Jae-Sik Chung ,  Sung-Min Sim ,  Dong-Hyeon Jang ,  Young-Hee Song ,  Seung-Kwan Ryu

Inventor： Myeong-Soon Park ,  Hyun-Soo Chung ,  In-Young Lee ,  Jae-Sik Chung ,  Sung-Min Sim ,  Dong-Hyeon Jang ,  Young-Hee Song ,  Seung-Kwan Ryu

IPC: H01L23/48 ,  H01L21/44

CPC classification number: H01L23/3114 ,  H01L23/525 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/02165 ,  H01L2224/02335 ,  H01L2224/02351 ,  H01L2224/05001 ,  H01L2224/05008 ,  H01L2224/05022 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05548 ,  H01L2224/05557 ,  H01L2224/05569 ,  H01L2224/10125 ,  H01L2224/13006 ,  H01L2224/13011 ,  H01L2224/13018 ,  H01L2224/13099 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/30105 ,  H01L2924/351 ,  H01L2924/00 ,  H01L2224/05599

Abstract: A wafer level chip scale package may have a gap provided between a solder bump and a bump land. The gap may be filled with a gas. A method of manufacturing a wafer level chip scale package may involve forming a redistribution line having a first opening, forming a seed metal layer having a second opening including an undercut portion, and forming the gap using the first and the second openings.

公开(公告)号：US20070164431A1

公开(公告)日：2007-07-19

申请号：US11549933

申请日：2006-10-16

Applicant: In Young LEE ,  Hyun-Soo CHUNG ,  Dong-Ho LEE ,  Sung-Min SIM ,  Dong-Soo SEO ,  Seung-Kwan RYU ,  Myeong-Soon PARK

Inventor： In Young LEE ,  Hyun-Soo CHUNG ,  Dong-Ho LEE ,  Sung-Min SIM ,  Dong-Soo SEO ,  Seung-Kwan RYU ,  Myeong-Soon PARK

IPC: H01L23/48 ,  H01L21/44

CPC classification number: H01L23/3114 ,  H01L23/5222 ,  H01L23/525 ,  H01L24/11 ,  H01L24/12 ,  H01L2224/0231 ,  H01L2224/02313 ,  H01L2224/0236 ,  H01L2224/024 ,  H01L2224/0401 ,  H01L2224/11334 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/30105 ,  H01L2924/351 ,  H01L2924/00

Abstract: A wafer level chip scale package capable of reducing parasitic capacitances between a rerouting and the metal wiring of a wafer, and a method for manufacturing the same are provided. An embodiment of the wafer level chip scale package includes a wafer arranged with a plurality of bonding pads and an insulating member formed on the wafer so that the bonding pads are exposed. A rerouting is further formed on the insulating member in contact with the exposed bonding pads and an external connecting terminal is electrically connected to a portion of the rerouting. Here, the insulating member overlapping the rerouting is provided with a plurality of spaces in which air is trapped.

Abstract translation: 提供能够降低重新布线和晶片的金属布线之间的寄生电容的晶片级芯片级封装及其制造方法。 晶片级芯片级封装的实施例包括具有多个接合焊盘的晶片和形成在晶片上的绝缘部件，使得焊盘露出。 在与暴露的接合焊盘接触的绝缘构件上进一步形成再路由，并且外部连接端子电连接到重新布线的一部分。 这里，与重新路由重叠的绝缘构件设置有空气被捕获的多个空间。

公开(公告)号：US20070108573A1

公开(公告)日：2007-05-17

申请号：US11448772

申请日：2006-06-08

Applicant: Hyun-Soo Chung ,  In-Young Lee ,  Dong-Hyeon Jang ,  Myeong-Soon Park ,  Dong-Ho Lee

Inventor： Hyun-Soo Chung ,  In-Young Lee ,  Dong-Hyeon Jang ,  Myeong-Soon Park ,  Dong-Ho Lee

IPC: H01L23/02

CPC classification number: H01L23/3114 ,  H01L23/525 ,  H01L24/02 ,  H01L24/11 ,  H01L24/12 ,  H01L2224/0231 ,  H01L2224/02311 ,  H01L2224/02313 ,  H01L2224/0401 ,  H01L2224/10126 ,  H01L2224/1191 ,  H01L2224/13022 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/3025

Abstract: A wafer level package may include a semiconductor substrate supporting an electrode pad. A first insulating layer may be provided on the semiconductor substrate. The first insulating layer may include a first opening through which the electrode pad may be exposed. A seed metal layer may be provided on an entire surface of the first insulating layer. A redistribution interconnection metal layer may be provided on the seed metal layer. A second insulating layer may be provided on the redistribution interconnection metal layer. The second insulating layer may have a second opening spaced from the first opening to expose a portion of the redistribution interconnection metal layer. The second insulating layer may surround the redistribution interconnection metal layer. An unwanted portion of seed metal layer may be removed using the second insulating layer as an etch mask.

Abstract translation: 晶片级封装可以包括支撑电极焊盘的半导体衬底。 第一绝缘层可以设置在半导体衬底上。 第一绝缘层可以包括第一开口，电极焊盘可以暴露在第一开口中。 种子金属层可以设置在第一绝缘层的整个表面上。 再分布互连金属层可以设置在种子金属层上。 第二绝缘层可以设置在再分布互连金属层上。 第二绝缘层可以具有与第一开口间隔开的第二开口，以暴露再分布互连金属层的一部分。 第二绝缘层可以包围再分布互连金属层。 可以使用第二绝缘层作为蚀刻掩模去除种子金属层的不需要的部分。

公开(公告)号：US20070096341A1

公开(公告)日：2007-05-03

申请号：US11430900

申请日：2006-05-10

Applicant: Hyun-soo Chung ,  Dong-hyeon Jang ,  Dong-ho Lee ,  In-young Lee

Inventor： Hyun-soo Chung ,  Dong-hyeon Jang ,  Dong-ho Lee ,  In-young Lee

IPC: H01L23/52

CPC classification number: H01L23/3128 ,  H01L23/13 ,  H01L23/49816 ,  H01L23/49833 ,  H01L24/48 ,  H01L24/97 ,  H01L2224/06136 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/4824 ,  H01L2224/73215 ,  H01L2224/92147 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01033 ,  H01L2924/09701 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19103 ,  H01L2224/85 ,  H01L2224/83 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2924/00

Abstract: A ball grid array type board on chip package may include an integrated circuit chip having an active surface that supports a plurality of contact pads. An interposer may be adhered to the active surface of the integrated circuit chip. At least one hole may be provided through the interposer to expose the contact pads. A board, which may have a first surface supporting a plurality of metal lines, may have a second surface adhered to the interposer. The board may have an opening through which the contact pads may be exposed. A plurality of bonding wires may connect the contact pads to the metal lines through the opening.

Abstract translation: 球栅阵列型片上芯片封装可以包括具有支撑多个接触焊盘的有源表面的集成电路芯片。 插入器可以粘附到集成电路芯片的有源表面。 可以通过插入件提供至少一个孔以暴露接触垫。 可以具有支撑多个金属线的第一表面的板可以具有粘附到插入件的第二表面。 板可以具有开口，接触垫可以穿过该开口露出。 多个接合线可以通过开口将接触垫连接到金属线。

公开(公告)号：US20070069320A1

公开(公告)日：2007-03-29

申请号：US11486041

申请日：2006-07-14

Applicant: In-Young Lee ,  Sung-Min Sim ,  Dong-Hyeon Jang ,  Hyun-Soo Chung ,  Jae-Sik Chung ,  Seung-Kwan Ryu ,  Myeong-Soon Park ,  Jong-Kook Yoon ,  Ju-Il Choi

Inventor： In-Young Lee ,  Sung-Min Sim ,  Dong-Hyeon Jang ,  Hyun-Soo Chung ,  Jae-Sik Chung ,  Seung-Kwan Ryu ,  Myeong-Soon Park ,  Jong-Kook Yoon ,  Ju-Il Choi

IPC: H01L31/00

CPC classification number: H01L24/12 ,  H01L23/3114 ,  H01L24/11 ,  H01L24/94 ,  H01L2224/0231 ,  H01L2224/0401 ,  H01L2224/05124 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/05671 ,  H01L2224/114 ,  H01L2224/1148 ,  H01L2224/116 ,  H01L2224/13099 ,  H01L2224/274 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2924/013

Abstract: A wiring structure may include a pad, a conductive pattern and an insulating photoresist structure. The pad may be provided on a body and electrically connected to a circuit unit of the body. The conductive pattern may be provided on the body and may be electrically connected to the pad. The insulating photoresist structure may be provided on a surface of the conductive pattern. The insulating photoresist structure may have a contact hole through which the conductive pattern may be partially exposed. The insulating photoresist structure may be fabricated by providing a photosensitive photoresist film on the conductive layer, and patterning the photosensitive photoresist film by two photo processes.

Abstract translation: 布线结构可以包括垫，导电图案和绝缘光致抗蚀剂结构。 垫可以设置在主体上并电连接到主体的电路单元。 导电图案可以设置在主体上并且可以电连接到垫。 绝缘光致抗蚀剂结构可以设置在导电图案的表面上。 绝缘光致抗蚀剂结构可以具有接触孔，导电图案可以通过该接触孔部分地暴露。 绝缘光致抗蚀剂结构可以通过在导电层上提供感光性光致抗蚀剂膜，并通过两个照相工艺对感光性光刻胶膜进行图案化来制造。