公开(公告)号：US07095065B2

公开(公告)日：2006-08-22

申请号：US10633504

申请日：2003-08-05

Applicant: Bin Yu ,  Shibly S. Ahmed ,  Haihong Wang

Inventor： Bin Yu ,  Shibly S. Ahmed ,  Haihong Wang

IPC: H01L29/80

CPC classification number: H01L29/785 ,  H01L27/1203 ,  H01L29/42392 ,  H01L29/66795

Abstract: A semiconductor device may include a substrate and an insulating layer formed on the substrate. A first device may be formed on the insulating layer, including a first fin. The first fin may be formed on the insulating layer and may have a first fin aspect ratio. A second device may be formed on the insulating layer, including a second fin. The second fin may be formed on the insulating layer and may have a second fin aspect ratio different from the first fin aspect ratio.

Abstract translation: 半导体器件可以包括衬底和形成在衬底上的绝缘层。 第一器件可以形成在绝缘层上，包括第一鳍片。 第一翅片可以形成在绝缘层上，并且可以具有第一翅片长宽比。 第二装置可以形成在绝缘层上，包括第二鳍片。 第二翅片可以形成在绝缘层上，并且可以具有与第一翅片长宽比不同的第二翅片长宽比。

公开(公告)号：US20060177998A1

公开(公告)日：2006-08-10

申请号：US11379435

申请日：2006-04-20

Applicant: Ming-Ren Lin ,  Witold Maszara ,  Haihong Wang ,  Bin Yu

Inventor： Ming-Ren Lin ,  Witold Maszara ,  Haihong Wang ,  Bin Yu

IPC: H01L21/3205

CPC classification number: H01L29/785 ,  H01L29/4908 ,  H01L29/66795 ,  H01L29/7842

Abstract: A method may include forming a gate electrode over a fin structure, depositing a first metal layer on a top surface of the gate electrode, performing a first silicide process to convert a portion of the gate electrode into a metal-silicide compound, depositing a second metal layer on a top surface of the metal-silicide compound, and performing a second silicide process to form a fully-silicided gate electrode.

Abstract translation: 一种方法可以包括在鳍结构上形成栅电极，在栅电极的顶表面上沉积第一金属层，执行第一硅化工艺以将栅电极的一部分转化为金属硅化物， 在金属硅化物化合物的顶表面上的金属层，并且执行第二硅化物处理以形成全硅化物栅电极。

公开(公告)号：US20060167662A1

公开(公告)日：2006-07-27

申请号：US11390895

申请日：2006-03-27

Applicant: Bin Yu ,  Yong Rui

Inventor： Bin Yu ,  Yong Rui

IPC: G06F11/30

CPC classification number: G06Q10/10

Abstract: An event-based system and process for recording and playback of collaborative electronic presentations is presented. The present system and process includes a technique for recording collaborative electronic presentations by capturing and storing the interactions between each participant and presentation data where each interaction event is timestamped and linked to a data file comprising the presentation data. The present system and process also includes a technique for playing back the recorded collaborative electronic presentation, which involves displaying the presentation data in an order it was originally presented and reproducing the recorded interactions between each participant and the displayed presentation data at the same point in the presentation that they were originally performed, based on the aforementioned timestamps.

公开(公告)号：US20060101022A1

公开(公告)日：2006-05-11

申请号：US10973185

申请日：2004-10-25

Applicant: Bin Yu ,  Yong Rui

Inventor： Bin Yu ,  Yong Rui

IPC: G06F17/30

CPC classification number: G06Q10/10

Abstract: A system and process for providing an interactive computer network-based virtual team worksite that combines data storage, team members' presence information, interaction tools and a past history log into one virtual complex is presented. Generally, this is accomplished by integrating a shared data module, a unique presence module and various conferencing tools such as a collaborative presentation module and chat module into a single worksite assessable over a distributed computer network. Thus, everything a team would need related to a project is available in this integrated place. A team member who logs onto the worksite can input data and commands using the worksite window sectors to interface with other team members also logged on to the worksite and to interact with the displayed data in the collaborative presentation sector.

Abstract translation: 提供了一种系统和过程，用于提供基于交互式计算机网络的虚拟团队工作现场，将数据存储，团队成员的存在信息，交互工具和过去历史记录结合到一个虚拟复合体中。 通常，这通过将共享数据模块，独特存在模块和诸如协作呈现模块和聊天模块的各种会议工具集成到通过分布式计算机网络可评估的单个工作现场来实现。 因此，一个团队需要与项目相关的一切都可以在这个集成的地方使用。 登录工地的团队成员可以使用工地窗口部门输入数据和命令，以便与登录到工作现场的其他团队成员进行交互，并与协作演示部门中显示的数据进行交互。

公开(公告)号：US06936506B1

公开(公告)日：2005-08-30

申请号：US10442975

申请日：2003-05-22

Applicant: James F. Buller ,  Derick J. Wristers ,  Qi Xiang ,  Bin Yu

Inventor： James F. Buller ,  Derick J. Wristers ,  Qi Xiang ,  Bin Yu

IPC: H01L21/336 ,  H01L21/8234 ,  H01L29/10

CPC classification number: H01L21/823807 ,  H01L29/1054

Abstract: A method of manufacturing a semiconductor device includes providing a strained-silicon semiconductor layer over a silicon germanium layer, and partially removing a first portion of the strained-silicon layer. The strained-silicon layer includes the first portion and a second portion, and a thickness of the second portion is greater than a thickness of the first portion. Initially, the first and second portions of the strained-silicon layer initially can have the same thickness. A p-channel transistor is formed over the first portion, and a n-channel transistor is formed over the second portion. A semiconductor device is also disclosed.

Abstract translation: 制造半导体器件的方法包括在硅锗层上提供应变硅半导体层，并部分去除应变硅层的第一部分。 应变硅层包括第一部分和第二部分，第二部分的厚度大于第一部分的厚度。 最初，应变硅层的第一和第二部分最初可以具有相同的厚度。 在第一部分上形成p沟道晶体管，并且在第二部分上形成n沟道晶体管。 还公开了一种半导体器件。

公开(公告)号：US06924561B1

公开(公告)日：2005-08-02

申请号：US10728910

申请日：2003-12-08

Applicant: Wiley Eugene Hill ,  Bin Yu

Inventor： Wiley Eugene Hill ,  Bin Yu

IPC: H01L21/336 ,  H01L21/8244 ,  H01L21/84 ,  H01L27/11 ,  H01L27/12 ,  H01L29/786

CPC classification number: H01L27/1108 ,  H01L21/845 ,  H01L27/11 ,  H01L27/1211 ,  H01L29/66803 ,  H01L29/785 ,  Y10S257/903 ,  Y10S438/944

Abstract: A memory device includes multiple fins formed adjacent to one another, a source region, a drain region, a gate, a wordline, and a bitline contact. At least one of the multiple fins is doped with a first type of impurities and at least one other one of the fins is doped with a second type of impurities. The source region is formed at one end of each of the fins and the drain region is formed at an opposite end of each of the fins. The gate is formed over two of the multiple fins, the wordline is formed over each of the multiple fins, and a bitline contact is formed adjacent at least one of the multiple fins.

Abstract translation: 存储器件包括彼此相邻形成的多个鳍，源极区，漏极区，栅极，字线和位线接触。 多个翅片中的至少一个被掺杂有第一类型的杂质，并且至少另外一个翅片掺杂有第二类型的杂质。 源区域形成在每个散热片的一端，并且漏极区域形成在每个散热片的相对端。 栅极形成在多个散热片的两个之上，字线形成在多个散热片的每一个上，并且与多个散热片中的至少一个相邻地形成有位线接触。

公开(公告)号：US06911697B1

公开(公告)日：2005-06-28

申请号：US10632965

申请日：2003-08-04

Applicant: Haihong Wang ,  Judy Xilin An ,  Bin Yu

Inventor： Haihong Wang ,  Judy Xilin An ,  Bin Yu

IPC: H01L21/336 ,  H01L29/423 ,  H01L29/786 ,  H01L27/01 ,  H01L29/76

CPC classification number: H01L29/785 ,  H01L29/42384 ,  H01L29/66818 ,  H01L29/7855 ,  H01L29/7856 ,  H01L29/78618

Abstract: A double-gate semiconductor device includes a substrate, an insulating layer, a fin, source and drain regions and a gate. The insulating layer is formed on the substrate and the fin is formed on the insulating layer. The source region is formed on the insulating layer adjacent a first side of the fin and the drain region is formed on the second side of the fin opposite the first side. The source and drain regions have a greater thickness than the fin in the channel region of the semiconductor device.

Abstract translation: 双栅极半导体器件包括衬底，绝缘层，鳍，源极和漏极区以及栅极。 绝缘层形成在基板上，并且鳍形成在绝缘层上。 源极区域形成在与鳍片的第一侧相邻的绝缘层上，并且漏极区域形成在与第一侧相对的翅片的第二侧上。 源极和漏极区域具有比半导体器件的沟道区域中的鳍片更大的厚度。

公开(公告)号：US06902966B2

公开(公告)日：2005-06-07

申请号：US09983625

申请日：2001-10-25

Applicant: Bin Yu ,  Robert B. Ogle ,  Eric N. Paton ,  Cyrus E. Tabery ,  Qi Xiang

Inventor： Bin Yu ,  Robert B. Ogle ,  Eric N. Paton ,  Cyrus E. Tabery ,  Qi Xiang

IPC: H01L21/28 ,  H01L21/20 ,  H01L21/265 ,  H01L21/268 ,  H01L21/336 ,  H01L29/417 ,  H01L29/78 ,  H01L21/00

CPC classification number: H01L29/665 ,  H01L21/268

Abstract: A method of manufacturing a MOSFET semiconductor device comprises forming a gate electrode over a substrate and a gate oxide between the gate electrode and the substrate; forming source/drain extensions in the substrate; forming first and second sidewall spacers; implanting dopants within the substrate to form source/drain regions in the substrate adjacent to the sidewalls spacers; laser thermal annealing to activate the source/drain regions; depositing a layer of nickel over the source/drain regions; and annealing to form a nickel silicide layer disposed on the source/drain regions. The source/drain extensions and sidewall spacers are adjacent to the gate electrode. The source/drain extensions can have a depth of about 50 to 300 angstroms, and the source/drain regions can have a depth of about 400 to 1000 angstroms. The annealing is at temperatures from about 350 to 500° C.

Abstract translation: 一种制造MOSFET半导体器件的方法包括：在栅极电极和衬底之间形成衬底上的栅电极和栅极氧化物; 在衬底中形成源极/漏极延伸部; 形成第一和第二侧壁间隔物; 在所述衬底内注入掺杂剂以在所述衬底中邻近所述侧壁间隔物形成源/漏区; 激光热退火激活源/漏区; 在源极/漏极区域上沉积镍层; 并退火以形成设置在源/漏区上的硅化镍层。 源极/漏极延伸部和侧壁间隔物与栅电极相邻。 源极/漏极延伸部可以具有约50至300埃的深度，并且源极/漏极区域可以具有约400至1000埃的深度。 退火温度在约350-500℃

公开(公告)号：US20050118824A1

公开(公告)日：2005-06-02

申请号：US11030191

申请日：2005-01-07

Applicant: Krishnashree Achuthan ,  Shibly Ahmed ,  Haihong Wang ,  Bin Yu

Inventor： Krishnashree Achuthan ,  Shibly Ahmed ,  Haihong Wang ,  Bin Yu

IPC: C09G1/02 ,  H01L21/3105 ,  H01L21/321 ,  H01L21/336 ,  H01L29/423 ,  H01L29/49 ,  H01L29/786 ,  H01L21/00 ,  H01L21/302 ,  H01L21/3205 ,  H01L21/461 ,  H01L21/4763 ,  H01L21/84

CPC classification number: H01L29/785 ,  C09G1/02 ,  H01L21/31053 ,  H01L21/3212 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/66795 ,  H01L29/6681 ,  Y10S438/959

Abstract: A method of manufacturing a MOSFET type semiconductor device includes planarizing a gate material layer that is deposited over a channel. The planarization is performed in a multi-step process that includes an initial “rough” planarization and then a “fine” planarization. The slurry used for the finer planarization may include added material that tends to adhere to low areas of the gate material.

Abstract translation: 制造MOSFET型半导体器件的方法包括平坦化沉积在沟道上的栅极材料层。 平面化在包括初始“粗糙”平坦化然后是“精细”平坦化的多步骤过程中进行。 用于更精细平坦化的浆料可以包括倾向于粘附到栅极材料的低区域的添加材料。

公开(公告)号：US06867101B1

公开(公告)日：2005-03-15

申请号：US09826472

申请日：2001-04-04

Applicant: Bin Yu

Inventor： Bin Yu

IPC: H01L21/28 ,  H01L21/314 ,  H01L21/318 ,  H01L29/49 ,  H01L29/51 ,  H01L21/336 ,  H01L21/31 ,  H01L21/3205

CPC classification number: H01L21/28194 ,  H01L21/28202 ,  H01L21/3141 ,  H01L21/3144 ,  H01L21/3185 ,  H01L29/4908 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518

Abstract: A method of fabricating a semiconductor device, having a nitride/high-k material/nitride gate dielectric stack with good thermal stability which does not diffuse into a silicon substrate, a polysilicon gate, or a polysilicon-germanium gate when experiencing subsequent high temperature processes, involving: (a) providing a substrate; (b) initiating formation of the nitride/high-k material/nitride gate dielectric stack by depositing a first ultra-thin nitride film on the substrate; (c) depositing a high-k material, such as a thin metal film, on the first ultra-thin nitride film; (d) depositing a second ultra-thin nitride film on the high-k material, thereby forming a sandwich structure; (e) completing formation of the nitride/high-k material/nitride gate dielectric stack from the sandwich structure; and (f) completing fabrication of the semiconductor device.

Abstract translation: 一种制造半导体器件的方法，其具有具有良好热稳定性的氮化物/高k材料/氮化物栅极电介质叠层，当经历随后的高温处理时，其不扩散到硅衬底，多晶硅栅极或多晶硅锗栅极 涉及：（a）提供底物; （b）通过在衬底上沉积第一超薄氮化物膜来引发氮化物/高k材料/氮化物栅极电介质叠层的形成; （c）在第一超薄氮化物膜上沉积诸如金属薄膜的高k材料; （d）在高k材料上沉积第二超薄氮化物膜，由此形成夹层结构; （e）从夹层结构完成氮化物/高k材料/氮化物栅极电介质堆叠的形成; 和（f）完成半导体器件的制造。