公开(公告)号：US07417250B1

公开(公告)日：2008-08-26

申请号：US11151550

申请日：2005-06-14

Applicant: James F. Buller ,  Derick J Wristers ,  Qi Xiang ,  Bin Yu

Inventor： James F. Buller ,  Derick J Wristers ,  Qi Xiang ,  Bin Yu

IPC: H01L29/04

CPC classification number: H01L21/823807 ,  H01L29/1054

Abstract: A method of manufacturing a semiconductor device includes providing a strained-silicon semiconductor layer over a silicon germanium layer, and partially removing a first portion of the strained-silicon layer. The strained-silicon layer includes the first portion and a second portion, and a thickness of the second portion is greater than a thickness of the first portion. Initially, the first and second portions of the strained-silicon layer initially can have the same thickness. A p-channel transistor is formed over the first portion, and a n-channel transistor is formed over the second portion. A semiconductor device is also disclosed.

Abstract translation: 制造半导体器件的方法包括在硅锗层上提供应变硅半导体层，并部分去除应变硅层的第一部分。 应变硅层包括第一部分和第二部分，第二部分的厚度大于第一部分的厚度。 最初，应变硅层的第一和第二部分最初可以具有相同的厚度。 在第一部分上形成p沟道晶体管，并且在第二部分上形成n沟道晶体管。 还公开了一种半导体器件。

公开(公告)号：US06936506B1

公开(公告)日：2005-08-30

申请号：US10442975

申请日：2003-05-22

Applicant: James F. Buller ,  Derick J. Wristers ,  Qi Xiang ,  Bin Yu

Inventor： James F. Buller ,  Derick J. Wristers ,  Qi Xiang ,  Bin Yu

IPC: H01L21/336 ,  H01L21/8234 ,  H01L29/10

CPC classification number: H01L21/823807 ,  H01L29/1054

Abstract: A method of manufacturing a semiconductor device includes providing a strained-silicon semiconductor layer over a silicon germanium layer, and partially removing a first portion of the strained-silicon layer. The strained-silicon layer includes the first portion and a second portion, and a thickness of the second portion is greater than a thickness of the first portion. Initially, the first and second portions of the strained-silicon layer initially can have the same thickness. A p-channel transistor is formed over the first portion, and a n-channel transistor is formed over the second portion. A semiconductor device is also disclosed.

Abstract translation: 制造半导体器件的方法包括在硅锗层上提供应变硅半导体层，并部分去除应变硅层的第一部分。 应变硅层包括第一部分和第二部分，第二部分的厚度大于第一部分的厚度。 最初，应变硅层的第一和第二部分最初可以具有相同的厚度。 在第一部分上形成p沟道晶体管，并且在第二部分上形成n沟道晶体管。 还公开了一种半导体器件。

公开(公告)号：US06764908B1

公开(公告)日：2004-07-20

申请号：US10173770

申请日：2002-06-19

Applicant: Daniel Kadosh ,  Derick J. Wristers ,  Qi Xiang ,  Bin Yu

Inventor： Daniel Kadosh ,  Derick J. Wristers ,  Qi Xiang ,  Bin Yu

IPC: H01L21336

CPC classification number: H01L29/1054 ,  H01L21/823807

Abstract: A method of manufacturing a semiconductor device comprises steps of: (a) providing a semiconductor substrate comprising an upper, tensilely strained lattice semiconductor layer and a lower, unstressed semiconductor layer; and (b) forming at least one MOS transistor on or within the tensilely strained lattice semiconductor layer, wherein the forming comprises a step of regulating the drive current of the at least one MOS transistor by adjusting the thickness of the tensilely strained lattice semiconductor layer. Embodiments include CMOS devices formed in substrates including a strained Si layer lattice-matched to a graded composition Si—Ge layer, wherein the thickness of the strained Si layer of each of the PMOS and NMOS transistors is adjusted to provide each transistor type with maximum drive current.

Abstract translation: 一种制造半导体器件的方法包括以下步骤：（a）提供包括上部，拉伸应变晶格半导体层和下部未应力半导体层的半导体衬底; 和（b）在拉伸应变晶格半导体层上或其内形成至少一个MOS晶体管，其中所述形成包括通过调整拉伸应变晶格半导体层的厚度来调节所述至少一个MOS晶体管的驱动电流的步骤。 实施例包括形成在包括与渐变组合物Si-Ge层晶格匹配的应变Si层的衬底中的CMOS器件，其中调节每个PMOS晶体管和NMOS晶体管的应变Si层的厚度以提供每个晶体管类型的最大驱动 当前。

公开(公告)号：US06689671B1

公开(公告)日：2004-02-10

申请号：US10151946

申请日：2002-05-22

Applicant: Bin Yu ,  Derick J. Wristers

Inventor： Bin Yu ,  Derick J. Wristers

IPC: H01L2120

CPC classification number: H01L29/6659 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/0251 ,  H01L21/02532 ,  H01L21/02667 ,  H01L21/26506 ,  H01L21/26513 ,  H01L29/78687

Abstract: A method of manufacturing a semiconductor device, comprising steps of: (a) providing a semiconductor substrate comprising a strained lattice semiconductor layer at an upper surface thereof and having a pre-selected amount of lattice strain; (b) forming a device structure in the semiconductor substrate by a process comprising forming at least one amorphous region in at least one portion of the strained lattice semiconductor layer; and (c) thermal annealing at a minimum temperature sufficient to effect epitaxial re-crystallization of the at least one amorphous region to re-form a strained lattice semiconductor layer having substantially the pre-selected amount of lattice strain, whereby strain relaxation of the strained lattice semiconductor arising from thermal annealing is substantially eliminated or minimized.

Abstract translation: 一种制造半导体器件的方法，包括以下步骤：（a）在其上表面提供包括应变晶格半导体层并具有预选量的晶格应变的半导体衬底;（b）在 半导体衬底，其包括在应变晶格半导体层的至少一部分中形成至少一个非晶区; 和（c）在足以实现所述至少一个非晶区域的外延再结晶的最小温度下的热退火以重新形成具有基本上预选量的晶格应变的应变晶格半导体层，由此应变松弛 基本消除或最小化由热退火产生的晶格半导体。

公开(公告)号：US07211489B1

公开(公告)日：2007-05-01

申请号：US10934378

申请日：2004-09-07

Applicant: Qi Xiang ,  Robert B. Ogle ,  Eric N. Paton ,  Cyrus E. Tabery ,  Bin Yu

Inventor： Qi Xiang ,  Robert B. Ogle ,  Eric N. Paton ,  Cyrus E. Tabery ,  Bin Yu

IPC: H01L21/336

CPC classification number: H01L21/268 ,  H01L21/26506 ,  H01L21/26586 ,  H01L29/1083 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/6659

Abstract: The present invention enables the production of improved high-reliability, high-density semiconductor devices. The present invention provides the high-density semiconductor devices by decreasing the size of semiconductor device structures, such as gate channel lengths. Short-channel effects are prevented by the use of highly localized halo implant regions formed in the device channel. Highly localized halo implant regions are formed by a tilt pre-amorphization implant and a laser thermal anneal of the halo implant region.

Abstract translation: 本发明能够制造改进的高可靠性，高密度的半导体器件。 本发明通过减小诸如栅极沟道长度的半导体器件结构的尺寸来提供高密度半导体器件。 通过使用在器件通道中形成的高度局部化的注入区来防止短沟道效应。 通过倾斜预非晶化植入和晕圈植入区域的激光热退火形成高度局部化的注入区域。

公开(公告)号：US06812106B1

公开(公告)日：2004-11-02

申请号：US10341366

申请日：2003-01-14

Applicant: Qi Xiang ,  Robert B. Ogle ,  Eric N. Paton ,  Cyrus E. Tabery ,  Bin Yu

Inventor： Qi Xiang ,  Robert B. Ogle ,  Eric N. Paton ,  Cyrus E. Tabery ,  Bin Yu

IPC: H01L21336

CPC classification number: H01L21/28194 ,  H01L21/26506 ,  H01L21/26586 ,  H01L21/268 ,  H01L29/517 ,  H01L29/66492 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66606

Abstract: Dopant deactivation of source/drain extensions during silicidation is reduced by forming deep source/drain regions using a disposable dummy gate as a mask, forming metal silicide layers on the deep source/drain regions, removing the dummy gate and then forming the source/drain extensions using laser thermal annealing. Embodiments include angular ion implantation, after removing the dummy gate, to form spaced apart pre-amorphized regions, ion implanting to form source/drain extension implants extending deeper into the substrate than the pre-amorphized regions, and then laser thermal annealing to activate the source/drain extensions having a higher impurity concentration at the main surface of the substrate than deeper into the substrate. Subsequent processing includes forming sidewall spacers, a gate dielectric layer and then the gate electrode.

Abstract translation: 通过使用一次性虚拟栅极作为掩模形成深源极/漏极区域，在深度源极/漏极区域形成金属硅化物层，去除虚拟栅极，然后形成源极/漏极 扩展使用激光热退火。 实施例包括角度离子注入，在去除虚拟栅极之后，形成间隔开的非晶化区域，离子注入以形成比预非晶化区域更深地延伸到衬底中的源极/漏极延伸植入物，然后激光热退火以激活 源/漏扩展在衬底的主表面具有较高的杂质浓度，而不是深入衬底。 随后的处理包括形成侧壁间隔物，栅介质层，然后形成栅电极。

公开(公告)号：US06680250B1

公开(公告)日：2004-01-20

申请号：US10145740

申请日：2002-05-16

Applicant: Eric N. Paton ,  Robert B. Ogle ,  Cyrus E. Tabery ,  Qi Xiang ,  Bin Yu

Inventor： Eric N. Paton ,  Robert B. Ogle ,  Cyrus E. Tabery ,  Qi Xiang ,  Bin Yu

IPC: H01L2144

CPC classification number: H01L29/6659 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/268

Abstract: A method of manufacturing a MOSFET semiconductor device includes forming a gate electrode over a substrate and a gate oxide between the gate electrode and the substrate. Inert dopants are then implanted within the substrate to form amorphized source/drain regions in the substrate extending to a first depth significantly greater than the intended junction depth. The amorphized source/drain regions are implanted with source/drain dopants such that the dopants extend into the substrate to a second depth less than the first depth, above and spaced apart from the end-of-range defect region created at the first depth by the amorphization process. Laser thermal annealing recrystallizes the amorphous regions, activates the source/drain regions and forms source/drain junctions. Because the recrystallization front velocity towards the substrate main surface is greater than the dopant atom velocity in the liquid substrate during laser thermal annealing, the junctions are not pushed down to the amorphous/crystalline silicon interface. Thus, end-of-range defects are located in a region below and spaced apart from the junctions, and the defects are not located in the activated source/drain regions. Junction leakage as a result of the end-of-range defects is thereby reduced.

Abstract translation: 一种制造MOSFET半导体器件的方法包括：在栅极电极和衬底之间在衬底上形成栅极电极和栅极氧化物。 然后将惰性掺杂剂注入衬底内以在衬底中形成非晶化的源极/漏极区域，延伸到明显大于预期结点深度的第一深度。 非晶化源极/漏极区域注入源极/漏极掺杂剂，使得掺杂剂延伸到衬底中的第二深度小于第一深度的第二深度，在第一深度之上，并且与在第一深度处产生的端部范围缺陷区域间隔开 非晶化过程。 激光热退火使非晶区再结晶，激活源极/漏极区并形成源极/漏极结。 因为朝向衬底主表面的再结晶前向速度大于激光热退火期间液体衬底中的掺杂剂原子速度，所以接合点不被推到非晶/硅晶界面。 因此，距离范围缺陷位于与接合点下方和间隔开的区域中，并且缺陷不位于活化的源极/漏极区域中。 因此，由于距离范围缺陷导致的结漏电减少。

公开(公告)号：US06657276B1

公开(公告)日：2003-12-02

申请号：US10163925

申请日：2002-06-06

Applicant: Olov B. Karlsson ,  HaiHong Wang ,  Bin Yu ,  Zoran Krivokapic ,  Qi Xiang

Inventor： Olov B. Karlsson ,  HaiHong Wang ,  Bin Yu ,  Zoran Krivokapic ,  Qi Xiang

IPC: H01L2900

CPC classification number: H01L29/7842 ,  H01L21/76264 ,  H01L21/76283 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/78654

Abstract: A shallow trench isolation region formed in a layer of semiconductor material. The shallow trench isolation region includes a trench formed in the layer of semiconductor material, the trench being defined by sidewalls and a bottom; a liner within the trench formed from a high-K material, the liner conforming to the sidewalls and bottom of the trench; and a fill section made from isolating material, and disposed within and conforming to the high-K liner. A method of forming the shallow trench isolation region is also disclosed.

Abstract translation: 形成在半导体材料层中的浅沟槽隔离区。 浅沟槽隔离区域包括形成在半导体材料层中的沟槽，沟槽由侧壁和底部限定; 由高K材料形成的沟槽内的衬垫，衬垫符合沟槽的侧壁和底部; 以及由隔离材料制成并填充并符合高K衬里的填充部分。 还公开了形成浅沟槽隔离区域的方法。

公开(公告)号：US06555879B1

公开(公告)日：2003-04-29

申请号：US10044247

申请日：2002-01-11

Applicant: Zoran Krivokapic ,  Qi Xiang ,  Bin Yu

Inventor： Zoran Krivokapic ,  Qi Xiang ,  Bin Yu

IPC: H01L2976

CPC classification number: H01L21/28194 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/4908 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518

Abstract: A MOSFET and method of fabrication. The MOSFET includes a metal containing source and a metal containing drain; a semiconductor body having a thickness of less than about 15 nm disposed between the source and the drain and on top of an insulating layer, the insulating layer formed on a substrate; a gate electrode disposed over the body and defining a channel interposed between the source and the drain; and a gate dielectric made from a high-K material and separating the gate electrode and the body.

Abstract translation: 一种MOSFET及其制造方法。 MOSFET包括含金属源和含金属的漏极; 设置在源极和漏极之间并且在绝缘层的顶部上具有小于约15nm的厚度的半导体本体，所述绝缘层形成在基板上; 栅电极，其设置在所述主体上并且限定插入在所述源极和所述漏极之间的沟道; 以及由高K材料制成并分离栅电极和主体的栅极电介质。

公开(公告)号：US06190952B1

公开(公告)日：2001-02-20

申请号：US09261273

申请日：1999-03-03

Applicant: Qi Xiang ,  Bin Yu

Inventor： Qi Xiang ,  Bin Yu

IPC: H01L2184

CPC classification number: H01L21/84 ,  H01L27/1203

Abstract: An ultra-large-scale integrated (ULSI) circuit includes MOSFETs which have different threshold voltages and yet have the same channel characteristics. The MOSFETs are provided on an SOI substrate. The thickness of a thin film on the substrate is varied to adjust the threshold voltage. The threshold voltage can be varied by roughly 240 mV. The thickness of the thin film can be adjusted through a LOCOS process.

Abstract translation: 超大规模集成（ULSI）电路包括具有不同阈值电压但具有相同通道特性的MOSFET。 MOSFET设置在SOI衬底上。 改变衬底上薄膜的厚度以调节阈值电压。 阈值电压可以改变大约240 mV。 薄膜的厚度可以通过LOCOS工艺进行调整。