公开(公告)号：US20230075011A1

公开(公告)日：2023-03-09

申请号：US17894989

申请日：2022-08-24

Applicant: POSTECH Research and Business Development Foundation

Inventor： Keehoon KIM ,  Dukchan YOON

IPC: B25J15/08

Abstract: A parallel-type gripper according to an embodiment of the present invention includes: a pair of jaws that are opposite to each other; and a parallel-type driving module in which the pair of jaws are movably connected in a horizontal direction such that they approach or move away from each other, and moving the pair of jaws in the horizontal direction so that the pair of jaws grip an object.

公开(公告)号：US20230074735A1

公开(公告)日：2023-03-09

申请号：US17675229

申请日：2022-02-18

Applicant: POSTECH Research and Business Development Foundation

Inventor： Seung Soo OH ,  Hye Bin Yoo

IPC: C12Q1/6823 ,  C12Q1/6853 ,  C12Q1/686

Abstract: The present invention relates to a metal ion-start DNA polymerase switch, a composition for isothermal polymerase amplification containing the same, and an isothermal amplification method using the metal ion-start DNA polymerase switch. The metal ion-start DNA polymerase switch according to the present invention may comprise: a binding module composed of TQ30 aptamer; a locking or unlocking module; and a catalytic module connecting between the binding module and the locking or unlocking module and composed of DNAzyme.

公开(公告)号：US20230048278A1

公开(公告)日：2023-02-16

申请号：US17571255

申请日：2022-01-07

Applicant: HYUNDAI MOTOR COMPANY ,  KIA CORPORATION ,  POSTECH RESEARCH AND BUSINESS DEVELOPMENT FOUNDATION

Inventor： Su-Jung Noh ,  Ji-Sung Lee ,  Han-Saem Lee ,  Joon-Hyun Kwon ,  Hyun-Sang Hwang ,  Woo-Seok Choi

IPC: G11C13/00 ,  G11C11/54 ,  G11C7/06 ,  G11C7/16

Abstract: A neuromorphic hardware apparatus based on a resistive memory array includes a resistive memory array in which a plurality of synaptic resistor elements are arranged. Each synaptic resistor element is changed in its resistance value depending on a voltage pulse applied thereto and stores the resistance value for a predetermined time. The apparatus also includes a neuron circuit configured to receive an output signal from the resistive memory array and to output a voltage signal to another resistive memory array. The neuron circuit includes a temperature compensation unit, which compensates for an output voltage of the resistive memory array on the basis of an operating temperature of the resistive memory array. Even when a resistive memory array outputs an abnormal output depending on an operating temperature, by compensating a neuron circuit for an input value, it is possible to prevent an operation error from occurring.

公开(公告)号：US11581834B2

公开(公告)日：2023-02-14

申请号：US17411921

申请日：2021-08-25

Applicant: Hyundai Motor Company ,  Kia Corporation ,  POSTECH Research and Business Development Foundation

Inventor： Hee Kwang Lee ,  Hyun Seok Hong ,  Kwang Hee Nam ,  Tae Yeon Lee

IPC: H02P21/00 ,  H02P21/22 ,  H02P21/18

Abstract: A method for determining a motor angle, may include deriving a sensor weight and a sensorless weight via a cross product of an actual current vector and a model-based sensored current vector and a cross product of the actual current vector and a model-based sensorless current vector; and determining a final motor angle by applying the sensor weight and the sensorless weight to each of a sensored angle and a sensorless angle.

公开(公告)号：US11552623B2

公开(公告)日：2023-01-10

申请号：US17560090

申请日：2021-12-22

Applicant: POSTECH Research and Business Development Foundation

Inventor： Jae Yoon Sim ,  Ki Seo Kang

IPC: H03K5/00 ,  H03K4/02 ,  H03K5/01 ,  H03M1/66 ,  H03K4/92

Abstract: The present disclosure provides a device and method of generating a nonlinear waveform signal dissipating low power and operating at a high speed. The device includes: a digital preprocessing unit configured to quantize an effective input signal to generate a linear data signal and a residual signal that is a difference between the effective input signal and the linear data signal; a nonlinear digital-to-analog conversion circuit (DAC) having a nonlinear relationship between an input and an output and configured to convert the linear data signal into a first analog signal; a linear interpolation DAC configured to convert the residual signal into a second analog signal to enable a generation of a converted analog signal by an addition of the second analog signal to the first analog signal; and an output circuit configured to output the converted analog signal as a nonlinear waveform signal.

公开(公告)号：US20220416083A1

公开(公告)日：2022-12-29

申请号：US17844873

申请日：2022-06-21

Applicant: POSTECH Research and Business Development Foundation

Inventor： Junwoo SON ,  Yunkyu PARK ,  DongKyu LEE ,  Si-Young CHOI ,  Hyeji SIM

IPC: H01L29/786 ,  H01L29/24 ,  H01L29/04 ,  H01L21/02

Abstract: Provided is an electronic device including a semiconductor substrate, a single-crystal first transition metal oxide layer on the semiconductor substrate, and a single-crystal second transition metal oxide layer spaced apart from the semiconductor substrate with the single-crystal first transition metal oxide layer interposed therebetween. The first transition metal oxide layer and the second transition metal oxide layer are in contact with each other. The semiconductor substrate, the first transition metal oxide layer, and the second transition metal oxide layer include different materials from each other. The first transition metal oxide layer and the second transition metal oxide layer have the same crystal direction.

公开(公告)号：US20220407072A1

公开(公告)日：2022-12-22

申请号：US17553947

申请日：2021-12-17

Applicant: POSTECH RESEARCH AND BUSINESS DEVELOPMENT FOUNDATION

Inventor： Moon Jeong PARK ,  Han Eol KANG

IPC: H01M4/60 ,  H01M10/0525 ,  C08F230/02

Abstract: The present disclosure relates to a cathode active material for a secondary battery, comprising a poly(S-co-VPA) vulcanized polymer, a preparation method thereof, and a lithium-sulfur secondary battery comprising the same.

公开(公告)号：US11533054B2

公开(公告)日：2022-12-20

申请号：US17489624

申请日：2021-09-29

Applicant: POSTECH Research and Business Development Foundation

Inventor： Seokhyeong Kang ,  Sunmean Kim ,  SungYun Lee ,  Sunghye Park

IPC: G06F7/50 ,  H03K19/0944 ,  H03K19/20 ,  G06F7/46

Abstract: A circuit includes a plurality of first counting gates, a first ternary half adder (THA) and a second THA that are connected to the plurality of first counting gates, a third THA configured to receive a sum output signal of the first THA and a sum output signal of the second THA, a first ternary sum gate configured to receive a carry output signal of the first THA and a carry output signal of the second THA, and a second ternary sum gate configured to receive a carry output signal of the third THA and an output signal of the first ternary sum gate, wherein the third THA and the second ternary sum gate may be configured to output voltage signals corresponding to a number of drain voltages among input signals applied to the plurality of first counting gates.

公开(公告)号：US20220357804A1

公开(公告)日：2022-11-10

申请号：US17704790

申请日：2022-03-25

Applicant: POSTECH RESEARCH AND BUSINESS DEVELOPMENT FOUNDATION

Inventor： Seung Moon CHOI ,  Gyeo Re YUN ,  Sang Yoon HAN

IPC: G06F3/0346 ,  A63F13/25 ,  A63F13/211 ,  G06F3/01 ,  G06T7/70 ,  G06T7/20 ,  G06T11/00

Abstract: A method of transforming a degree of freedom (DoF) in a multiple sensorial media (mulsemedia) system includes detecting, by a motion detector, a motion of an object to which motion effects are to be provided; calculating, by a motion proxy calculator, a motion proxy corresponding to the motion of the object; and transforming, by a transformer, the motion proxy into a motion command implementable within a motion range of a motion platform.

公开(公告)号：US20220350568A1

公开(公告)日：2022-11-03

申请号：US17489629

申请日：2021-09-29

Applicant: Postech Research and Business Development Foundation

Inventor： Seokhyeong KANG ,  Sunmean KIM ,  Sunghye PARK ,  SungYun LEE

IPC: G06F7/502 ,  H03K19/173

Abstract: A circuit includes a first full adder, a second full adder, a first half adder, a third full adder configured to receive a sum output signal of the first full adder, a sum output signal of the second full adder, and a sum output signal of the first half adder, a fourth full adder configured to receive a carry output signal of the first full adder, a carry output signal of the second full adder, and a carry output signal of the first half adder, a second half adder configured to receive a carry output signal of the third full adder and a sum output signal of the fourth full adder, and a third half adder configured to receive a carry output signal of the second half adder and a carry output signal of the fourth full adder.