公开(公告)号：US10254342B2

公开(公告)日：2019-04-09

申请号：US15508168

申请日：2014-11-26

Applicant: Renesas Electronics Corporation

Inventor： Yoichi Maeda ,  Susumu Abe ,  Yoshitaka Taki

IPC: G01R31/00 ,  G01R31/3183 ,  G01R31/3181 ,  G06F11/25 ,  G01R31/3187 ,  G01R31/317

Abstract: A semiconductor device includes a first circuit and a plurality of pattern generators connected to the first circuit and each supplying a test pattern to the first circuit. A pattern-generator control circuit controls each of the plurality of pattern generators such that the pattern generator starts to operate when a control signal is at a first level and the pattern generator stops operating when the control signal is not at the first level. A pattern compressor compresses a result output from the first circuit in response to supply of the test patterns from the plurality of pattern generators. A pattern-compressor control circuit controls the pattern compressor. A self-diagnosis control circuit is connected to the pattern-generator control circuit and the pattern-compressor control circuit and controls the pattern-generator control circuit such that stop timings of the test patterns differ from one another among the plurality of pattern generators due to changing the control signals to selectively stop the pattern generators in a predetermined manner.

公开(公告)号：US20180364309A1

公开(公告)日：2018-12-20

申请号：US15806666

申请日：2017-11-08

Applicant: International Business Machines Corporation

Inventor： Thomas Gentner ,  Daniel Rodko ,  Hagen Schmidt ,  Otto A. Torreiter

IPC: G01R31/3185 ,  G01R31/3187 ,  G01R31/317

CPC classification number: G01R31/318552 ,  G01R31/31727 ,  G01R31/3187

Abstract: An integrated circuit with a hardware-based controller enables a system for a set of clock cycles and selectively enables an aspect of the system for a subset of the set of clock cycles. The controller includes a clock cycle select circuit to output a test select signal that indicates the subset of the set of clock cycles during which to enable the aspect of the system, and a test start circuit to receive the test select signal and output a test signal to the system to enable the system for the set of clock cycles. The controller also includes an AND gate to output a gated signal to enable the aspect of the system for the subset of the set of clock cycles based on the test select signal.

公开(公告)号：US10088524B2

公开(公告)日：2018-10-02

申请号：US14987848

申请日：2016-01-05

Applicant: International Business Machines Corporation

Inventor： Satya R. S. Bhamidipati ,  Raghu G. Gopalakrishnasetty ,  Mary P. Kusko ,  Cedric Lichtenau

IPC: G01R31/28 ,  G01R31/3177 ,  G01R31/317 ,  G01R31/3183 ,  G01R31/3185 ,  G01R31/3187

Abstract: Aspects include a system having logic built-in self-test (LBIST) circuitry for use in an integrated circuit with scan chains. The system includes a pattern generator configured for generating scan-in test values for said scan chains; a signature register configured for collecting scan-out responses from said scan chains after a clock sequence; an on-product control generator configured for controlling at least one test parameter; one or more microcode array or memory elements configured to receive inputs to initialize fields in the microcode array or memory elements; and a test controller. The test controller includes a reader component configured for reading test parameters from a field of the microcode array or the memory elements; and a programming component configured for configuring the on-product control generator and the pattern generator with a LBIST pattern according to the read test parameters.

公开(公告)号：US10088519B1

公开(公告)日：2018-10-02

申请号：US15486388

申请日：2017-04-13

Applicant: International Business Machines Corporation

Inventor： David M. Friend ,  Grant P. Kesselring ,  Eric J. Lukes ,  James D. Strom

IPC: G01R31/3187 ,  G01R31/28 ,  H01L21/66 ,  H03L7/08

Abstract: The present disclosure discloses an IC with an electromigration (EM) monitor. The IC includes a functional circuit configured according to a first value of a parameter related to EM tolerance. The IC also includes a dummy version of the functional circuit configured according to a second value of the parameter. The second value causes the dummy version of the functional circuit to be more sensitive to an EM event than the functional circuit. Upon the EM monitor determines that the EM event occurs in the dummy version of the functional circuit, the EM monitor asserts a signal indicating that the EM event has occurred in the dummy version of the functional circuit and providing a warning that the EM event is likely to occur in the functional circuit.

公开(公告)号：US10036770B2

公开(公告)日：2018-07-31

申请号：US14924438

申请日：2015-10-27

Applicant: SK hynix Inc.

Inventor： Yong-Ho Kong

IPC: G01R31/3187 ,  G01R31/26 ,  G01R31/317

CPC classification number: G01R31/2607 ,  G01R31/2644 ,  G01R31/31701 ,  G01R31/31724

Abstract: A semiconductor device includes a plurality of test entry selection units configured to selectively activate a plurality of test entry signals in response to a test entry code, and a plurality of test operation blocks, corresponding to the respective test entry signals, each configured to be reset in response to activation of the corresponding test entry signal to perform a set test operation corresponding to a test selection code.

公开(公告)号：US20180203061A1

公开(公告)日：2018-07-19

申请号：US15584500

申请日：2017-05-02

Applicant: Texas Instruments Incorporated

Inventor： Sam Gnana Sabapathy

IPC: G01R31/28 ,  G01R31/3177 ,  G01R31/3187 ,  G06F17/50 ,  H01L21/22 ,  H01L21/70 ,  H01L29/06

CPC classification number: H01L21/70 ,  G01R31/31716 ,  G01R31/3187 ,  G06F17/5045

Abstract: A packaged integrated circuit (IC) chip that provides input/output (I/O) signal fail safe verification is disclosed. The packaged IC chip includes a first processing unit, a first control peripheral coupled to receive a first processed signal from the processing unit and to provide an output signal, and compare logic. The compare logic is coupled to receive the output signal and a comparison signal, to compare the output signal and the comparison signal, and to provide an error signal responsive to a difference between the output signal and the comparison signal.

公开(公告)号：US09984766B1

公开(公告)日：2018-05-29

申请号：US15467042

申请日：2017-03-23

Applicant: ARM Limited

Inventor： Alan Jeremy Becker ,  Peter Logan Harrod

IPC: G11C29/12 ,  G01R31/3187 ,  G06F11/08 ,  G06F12/14

CPC classification number: G11C29/12 ,  G01R31/3187 ,  G06F11/08 ,  G06F12/1433 ,  G06F2212/1052 ,  G11C29/16 ,  G11C2029/0409

Abstract: A data processing apparatus includes a memory and memory protection circuitry for providing an operational path to the memory during operational use of the memory. A memory built-in self-test controller 34 performs built-in self-test operations upon the memory using either an indirect test access path to the memory via the memory protection circuitry or a direct test access path to the memory which bypasses the memory protection circuitry. Thus, the correct operation of the memory protection circuitry itself can be tested in addition to the correct operation of the memory.

公开(公告)号：US09983262B1

公开(公告)日：2018-05-29

申请号：US15198217

申请日：2016-06-30

Applicant: AMAZON TECHNOLOGIES, INC.

Inventor： Dan Trock ,  Ron Diamant

IPC: G01R31/28 ,  G01R31/317 ,  G01R31/3187 ,  G01R31/3177 ,  G01R31/3185

CPC classification number: G01R31/31724 ,  G01R31/3177 ,  G01R31/318525 ,  G01R31/31853 ,  G01R31/3187

Abstract: A device includes one or more random number generator (RNG) cores (e.g., true random number generator cores) and a built-in self-test controller (BIST) configured to perform various fault tests on each RNG core. The tests include a stuck-at-1 fault test, a stuck-at-0 fault test, and a transition delay fault test. For those RNG cores that have multiple ring oscillators, each individual ring oscillator is fault tested by the BIST controller. For those RNG cores that have a multi-tap inverter chain configuration, the individual taps may be tested by the BIST controller. The RNG core also may comprise a bi-stable cell which can be tested by the BIST controller as well.

公开(公告)号：US09797938B2

公开(公告)日：2017-10-24

申请号：US14228472

申请日：2014-03-28

Applicant: International Business Machines Corporation

Inventor： Jose A. Hejase ,  Nanju Na ,  Nam H. Pham ,  Lloyd A. Walls

IPC: G01R29/26 ,  G01R31/00 ,  G01R31/3187

CPC classification number: G01R29/26 ,  G01R31/001 ,  G01R31/3187

Abstract: Functionality for estimating characteristics of an on-chip noise signal can be implemented on a processing module. An on-chip noise signal is determined at an on-chip determination point of a computer chip. The on-chip noise signal is converted to a frequency-varying signal using a voltage-controlled oscillator implemented on the computer chip. The frequency-varying signal is measured at an off-chip measurement point and frequency information is extracted from the frequency-varying signal. The frequency information is converted to a voltage level associated with the on-chip noise signal based on the relationship between an input voltage provided to the voltage-controlled oscillator and an output frequency generated by the voltage-controlled oscillator.

公开(公告)号：US09791503B1

公开(公告)日：2017-10-17

申请号：US14871411

申请日：2015-09-30

Applicant: Integrated Device Technology, Inc.

Inventor： James Bryan Northcutt ,  Stephen Amar Tibbitts ,  Robert A. Gubser ,  Bruce Edward Clark ,  John William Fallisgaard ,  Kenneth Astrof

IPC: G01R31/3187 ,  G01R31/28 ,  H03B5/32

CPC classification number: G01R31/2884 ,  G01R31/282 ,  G01R31/2836 ,  G01R31/2853 ,  H03B5/04 ,  H03B5/32 ,  H03B5/36 ,  H03H9/02133 ,  H03H9/02834 ,  H03H9/02897 ,  H03H9/0547 ,  H03H9/10 ,  H03H9/1021 ,  H03H9/13 ,  H03H9/205 ,  H03H11/44

Abstract: Packaged integrated circuit devices include an oscillator circuit having a resonator (e.g., quartz crystal, MEMs, etc.) associated therewith, which is configured to generate a periodic reference signal. A built-in self-test (BIST) circuit is provided, which is selectively electrically coupled to first and second terminals of the resonator during an operation by the BIST circuit to test at least one performance characteristic of the resonator, such as at least one failure mode. These test operations may occur during a built-in self-test time interval when the oscillator circuit is at least partially disabled. In this manner, built-in self-test circuitry may be utilized to provide an efficient means of testing a resonating element/structure using circuitry that is integrated within an oscillator chip and within a wafer-level chip-scale package (WLCSP) containing the resonator.