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    SPACER-DEFINED BACK-END TRANSISTOR AS MEMORY SELECTOR
    45.
    发明申请
    SPACER-DEFINED BACK-END TRANSISTOR AS MEMORY SELECTOR 有权

    公开(公告)号：US20240381669A1

    公开(公告)日：2024-11-14

    申请号：US18781186

    申请日：2024-07-23

    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

    Inventor： Ken-Ichi Goto ,  Chung-Te Lin ,  Mauricio Manfrini

    IPC: H10B61/00 ,  H10B63/00

    Abstract: The present disclosure, in some embodiments, relates to a memory device. In some embodiments, the memory device comprises a substrate and a lower interconnect metal layer disposed over the substrate. A selecting transistor is disposed over the lower interconnect metal layer. A memory cell is disposed over the selecting transistor and comprises a bottom electrode electrically connected to the selecting transistor, a data storage structure disposed over the bottom electrode, and a top electrode disposed over the data storage structure.

    Three dimensional stacked semiconductor memory
    47.
    发明授权
    Three dimensional stacked semiconductor memory 有权

    公开(公告)号：US12144189B2

    公开(公告)日：2024-11-12

    申请号：US17939859

    申请日：2022-09-07

    Applicant: Kioxia Corporation

    Inventor： Hidehiro Shiga ,  Daisaburo Takashima

    IPC: G11C11/00 ,  G11C11/16 ,  G11C13/00 ,  H10B61/00 ,  H10B63/00 ,  H10N50/80 ,  H10N70/00

    Abstract: According to a certain embodiment, the 3D stacked semiconductor memory includes: a first electrode line extending in a first direction orthogonal to the semiconductor substrate; a second electrode line adjacent to the first electrode line in a second direction orthogonal to the first direction, and extending in the first direction; a first variable resistance film extending in the first direction and in contact with the second electrode line; a first semiconductor film in contact with the first variable resistance film and the first electrode line; a first potential applying electrode extending in the second direction and in contact with a first insulator layer; a second semiconductor film in contact with a second variable resistance film and the first electrode line; and a second potential applying electrode extending in the second direction and in contact with a second insulator layer. The first and second potential applying electrodes are electrically different nodes.

    Multitier arrangements of integrated devices, and methods of forming sense/access lines
    48.
    发明授权
    Multitier arrangements of integrated devices, and methods of forming sense/access lines 有权

    公开(公告)号：US12144188B2

    公开(公告)日：2024-11-12

    申请号：US18099777

    申请日：2023-01-20

    Applicant: Micron Technology, Inc.

    Inventor： Lei Wei ,  Hongqi Li

    IPC: H01L23/528 ,  H10B63/00 ,  H10N70/00 ,  H10N70/20

    Abstract: Some embodiments include an arrangement having a memory tier with memory cells on opposing sides of a coupling region. First sense/access lines are under the memory cells, and are electrically connected with the memory cells. A conductive interconnect is within the coupling region. A second sense/access line extends across the memory cells, and across the conductive interconnect. The second sense/access line has a first region having a second conductive material over a first conductive material, and has a second region having only the second conductive material. The first region is over the memory cells, and is electrically connected with the memory cells. The second region is over the conductive interconnect and is electrically coupled with the conductive interconnect. An additional tier is under the memory tier, and includes CMOS circuitry coupled with the conductive interconnect. Some embodiments include methods of forming multitier arrangements.

    Variable-resistance memory device
    49.
    发明授权
    Variable-resistance memory device 有权

    公开(公告)号：US12144186B2

    公开(公告)日：2024-11-12

    申请号：US17345776

    申请日：2021-06-11

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Jaehun Lee ,  Youngcheon Jeong

    IPC: H01L45/00 ,  H10B63/00 ,  H10N70/00 ,  H10N70/20

    Abstract: A variable-resistance memory device includes a substrate, an insulating layer disposed on the substrate and having a contact hole, a contact structure filling a lower region of the contact hole, a first electrode layer having a first portion disposed on the contact structure and a second portion extending to a side wall of an upper region of the contact hole, a variable-resistance layer covering the first electrode layer in the upper region of the contact hole, a sidewall spacer disposed between the second portion of the first electrode layer and the variable-resistance layer in the upper region of the contact hole, and a second electrode layer disposed on the variable-resistance layer in the upper region of the first contact hole.

    SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE
    50.
    发明申请
    SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE 有权

    公开(公告)号：US20240373765A1

    公开(公告)日：2024-11-07

    申请号：US18777380

    申请日：2024-07-18

    Applicant: SK Hynix Inc.

    Inventor： Ji Sun HAN

    IPC: H10N70/00 ,  H10B63/00 ,  H10N70/20

    Abstract: A semiconductor device includes: a first electrode including a carbon layer; a second electrode; a variable resistance layer interposed between the first electrode and the second electrode; and a barrier layer interposed between the first electrode and the variable resistance layer, the barrier layer including nitrogen and carbon. A concentration of the nitrogen in the barrier layer is equal to or higher than that of the carbon in the barrier layer.

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