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公开(公告)号：US09691852B2
公开(公告)日：2017-06-27
申请号：US14704355
申请日：2015-05-05
发明人： Shigeo Tokumitsu
IPC分类号： H01L29/06 , H01L29/861 , H01L29/66 , H01L29/78 , H01L29/10 , H01L27/092
CPC分类号： H01L21/76229 , H01L23/528 , H01L27/0922 , H01L29/0619 , H01L29/0649 , H01L29/0653 , H01L29/0692 , H01L29/1045 , H01L29/1083 , H01L29/1087 , H01L29/66659 , H01L29/7835 , H01L29/8611
摘要： An element isolation trench is formed in a substrate and is formed along each side of a polygon in a planar view. A first trench is formed in the substrate and extends in a direction different from that of any side of the trench. A first-conductivity type region is formed on/over apart located on the side of an end of the first trench in the substrate. Accordingly, when an impurity region that extends in a depth direction in the substrate is formed by forming the trench in the substrate and diagonally implanting an impurity into the trench, the impurity is prevented from being implanted into a side face of a groove such as a groove for element isolation and so forth impurity implantation into the side face of which is not desired.
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公开(公告)号：US09691604B2
公开(公告)日：2017-06-27
申请号：US14808026
申请日：2015-07-24
发明人： Yong Cheng , Xianyong Pu , Haiqiang Wang
IPC分类号： H01L29/66 , H01L21/02 , H01L29/78 , H01L29/06 , H01L21/762 , H01L29/08 , H01L21/265 , H01L29/10
CPC分类号： H01L21/02164 , H01L21/26513 , H01L21/26586 , H01L21/76224 , H01L21/76229 , H01L29/0653 , H01L29/0847 , H01L29/1045 , H01L29/66659 , H01L29/7835
摘要： A LDMOS transistor includes a semiconductor substrate with a first doping type; a plurality of first trenches formed in the semiconductor substrate; a wave-shaped drift region with an increased conductive path and a second doping type formed on the semiconductor substrate between adjacent first trenches and the semiconductor substrate exposed by side and bottom surfaces of the first trenches; a first shallow trench isolation (STI) structure formed in each of the first trenches; a body region with the first doping type formed in semiconductor substrate at one side of the drift region; a gate structure formed over portions of the body region, the drift region and the first STI structure most close to the body region; a source region formed in the body region; and a drain region formed in the drift region at one side of the first STI structure most far away from the body region.
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公开(公告)号：US09673319B2
公开(公告)日：2017-06-06
申请号：US15066946
申请日：2016-03-10
发明人： Farshid Iravani , Jan Nilsson
IPC分类号： H01L29/66 , H01L29/78 , H01L21/762 , H01L29/06 , H01L29/40 , H01L29/423 , H02M3/156 , H01L29/10
CPC分类号： H01L29/7816 , H01L21/76202 , H01L29/0649 , H01L29/0653 , H01L29/1045 , H01L29/1083 , H01L29/1095 , H01L29/402 , H01L29/4238 , H01L29/66681 , H01L29/7835 , H02M3/156
摘要： A slotted gate power transistor is a lateral power device including a substrate, a gate dielectric formed over the substrate, a channel region in the substrate below the gate dielectric and gate electrode layer formed over the gate dielectric. The gate electrode layer overlaps the gate dielectric above the channel region, an accumulation region, and a drift region below an oxide filled shallow trench isolation (or STI) or locally oxidized silicon (LOCOS) region. The slotted gate power transistor includes one or more slots or openings on the gate electrode layer over the accumulation region. Electrical connectivity is maintained over the entire gate electrode layer without external wiring.
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公开(公告)号：US20170148784A1
公开(公告)日：2017-05-25
申请号：US14948449
申请日：2015-11-23
发明人： Shuming Xu , Wenhua Dai
CPC分类号： H01L27/0629 , H01L21/8234 , H01L23/5227 , H01L23/645 , H01L27/0617 , H01L28/10 , H01L28/60 , H01L29/1045 , H01L29/402 , H01L29/4175 , H01L29/66484 , H01L29/66659 , H01L29/66681 , H01L29/7817 , H01L29/7831 , H01L29/7835
摘要： A method of integrating at least one passive component and at least one active power device on a same substrate includes: forming a substrate having a first resistivity value associated therewith; forming a low-resistivity region having a second resistivity value associated therewith in the substrate, the second resistivity value being lower than the first resistivity value; forming the at least one active power device in the low-resistivity region; forming an insulating layer over at least a portion of the at least one active power device; and forming the at least one passive component on an upper surface of the insulating layer above the substrate having the first resistivity value, the at least one passive component being disposed laterally relative to the at least one active power device and electrically connected with the at least one active power device.
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公开(公告)号：US09660044B2
公开(公告)日：2017-05-23
申请号：US14916511
申请日：2013-09-05
IPC分类号： H01L29/78 , H01L29/49 , H01L29/66 , H01L29/423 , H01L29/10
CPC分类号： H01L29/4983 , H01L29/1045 , H01L29/1095 , H01L29/42356 , H01L29/42368 , H01L29/42376 , H01L29/66712 , H01L29/66719 , H01L29/7802
摘要： A power field effect transistor, a power field effect transistor device and a method of manufacturing a power field effect transistor are provided. During the manufacturing of the power field effect transistor, a body drive stage to manufacture the body region of the power field effect transistor is shortened to obtain a relatively low on resistance for the power field effect transistor. Before the implanting stage of the dopants of the body region, a pre body drive stage is introduced. During the pre body drive stage and the body drive stage sidewalls of a polysilicon layer of the power field effect transistor are oxidized to obtain a power field effect transistor which has at the sidewalls an oxidized polysilicon layer that is thick enough to prevent a premature current injection from the gate to the source regions of the power field effect transistor.
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公开(公告)号：US09653558B2
公开(公告)日：2017-05-16
申请号：US14739702
申请日：2015-06-15
发明人： Shih-Yin Hsiao , Kai-Kuen Chang , Kun-Huang Yu
IPC分类号： H01L27/088 , H01L29/40 , H01L21/762 , H01L29/66 , H01L29/78 , H01L29/06 , H01L29/423 , H01L29/10
CPC分类号： H01L29/404 , H01L21/762 , H01L23/485 , H01L23/522 , H01L29/0653 , H01L29/1045 , H01L29/42368 , H01L29/66659 , H01L29/7835
摘要： A semiconductor structure and a manufacturing method thereof are provided. The semiconductor structure includes a substrate, a source region, a drain region, a gate, and a dummy contact. The source region and the drain region are formed in the substrate. The gate is formed on the substrate and between the source region and the drain region. The dummy contact includes a plurality of dummy plugs formed on the substrate, wherein the dummy plugs have depths decreasing towards the drain region.
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公开(公告)号：US09640524B2
公开(公告)日：2017-05-02
申请号：US14924708
申请日：2015-10-27
发明人： Chung-Yu Huang , Kuan-Cheng Su , Tien-Hao Tang , Ping-Jui Chen , Po-Ya Lai
IPC分类号： H01L23/62 , H01L27/02 , H01L27/088
CPC分类号： H01L27/0277 , H01L27/0259 , H01L27/0886 , H01L29/0619 , H01L29/0649 , H01L29/0653 , H01L29/0847 , H01L29/1045 , H01L29/42372 , H01L29/7816 , H01L29/7835 , H01L29/7851
摘要： An ESD protection semiconductor device includes a substrate, a gate set formed on the substrate, a source region and a drain region formed in the substrate respectively at two sides of the gate set, at least a first doped region formed in the source region, and at least a second doped region formed in the drain region. The source region, the drain region and the second doped region include a first conductivity type, and the first doped region includes a second conductivity type. The first conductivity type and the second conductivity type are complementary to each other. The second doped region is electrically connected to the first doped region.
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公开(公告)号：US09627520B2
公开(公告)日：2017-04-18
申请号：US15009096
申请日：2016-01-28
IPC分类号： H01L29/739 , H01L29/10 , H01L29/66 , H01L29/78 , H01L29/861 , H01L29/872 , H01L29/06 , H01L29/40 , H01L29/423
CPC分类号： H01L29/7397 , H01L29/0615 , H01L29/0623 , H01L29/0653 , H01L29/0661 , H01L29/0696 , H01L29/0878 , H01L29/1045 , H01L29/105 , H01L29/1095 , H01L29/404 , H01L29/407 , H01L29/42376 , H01L29/66674 , H01L29/66734 , H01L29/7801 , H01L29/7802 , H01L29/7811 , H01L29/7813 , H01L29/861 , H01L29/872
摘要： A semiconductor component is disclosed. One embodiment includes a semiconductor body including a first semiconductor layer having at least one active component zone, a cell array with a plurality of trenches, and at least one cell array edge zone. The cell array edge zone is only arranged in an edge region of the cell array, adjoining at least one trench of the cell array, and being at least partially arranged below the at least one trench in the cell array.
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公开(公告)号：US09614074B1
公开(公告)日：2017-04-04
申请号：US15076617
申请日：2016-03-21
发明人： Xin Lin , Hongning Yang , Jiang-Kai Zuo
IPC分类号： H01L29/78 , H01L29/66 , H01L29/10 , H01L29/06 , H01L21/265
CPC分类号： H01L29/063 , H01L21/761 , H01L29/0623 , H01L29/0653 , H01L29/1045 , H01L29/1083 , H01L29/66659 , H01L29/7835
摘要： A device includes a semiconductor substrate, a buried doped isolation layer disposed in the semiconductor substrate to isolate the device, a body region disposed in the semiconductor substrate and to which a voltage is applied during operation and in which a channel is formed during operation, and a depletion region disposed in the semiconductor substrate and having a conductivity type in common with the buried doped isolation barrier and the body region. The depletion region reaches a depth in the semiconductor substrate to be in contact with the buried doped isolation layer. The depletion region establishes an electrical link between the buried doped isolation layer and the body region such that the buried doped isolation layer is biased at a voltage level lower than the voltage applied to the body region.
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公开(公告)号：US20170092754A1
公开(公告)日：2017-03-30
申请号：US15164677
申请日：2016-05-25
发明人： Tsutomu INA , Tohru OKA
IPC分类号： H01L29/778 , H01L29/205 , H01L29/10 , H02M1/42 , H01L29/66 , H02M7/00 , H02M7/06 , H02M1/08 , H01L29/20 , H01L29/423
CPC分类号： H01L29/7787 , H01L29/0878 , H01L29/1045 , H01L29/1095 , H01L29/2003 , H01L29/205 , H01L29/4236 , H01L29/66462 , H01L29/7813 , H02M1/08 , H02M1/42 , H02M1/4225 , H02M7/003 , H02M7/06 , Y02B70/126
摘要： There is provided a semiconductor device comprising a substrate, a first semiconductor layer, a second semiconductor layer, a third semiconductor layer, a trench and an insulating film arranged to cover a surface of the trench. The first semiconductor layer has a carrier concentration that provides a peak in a thickness direction perpendicular to a plane direction. A high carrier concentration area having a peak of the carrier concentration in the first semiconductor layer is extended in the plane direction at a location away from the trench to be located on the substrate side of the trench. This configuration reduces the on resistance while suppressing reduction of the breakdown voltage in the semiconductor device.
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