公开(公告)号：US20120099386A1

公开(公告)日：2012-04-26

申请号：US13183641

申请日：2011-07-15

Applicant: Byoung Sung YOO ,  Chang Won YANG

Inventor： Byoung Sung YOO ,  Chang Won YANG

IPC: G11C7/10

CPC classification number: G11C16/0483 ,  G11C2216/14

Abstract: A semiconductor memory device includes memory cells for storing data, page buffers each configured to comprise a dynamic latch and a static latch on which data to be programmed in to the memory cells or data read from the memory cells are latched, and a control logic configured to store a plurality of refresh mode select codes corresponding to various refresh cycles, and refresh the dynamic latch by exchanging data between the static latch and the dynamic latch according to a refresh cycle corresponding to a selected refresh mode select code.

Abstract translation: 半导体存储器件包括用于存储数据的存储器单元，每个被配置为包括动态锁存器和静态锁存器的页缓冲器，在其上锁存要被编程到存储器单元的数据或从存储器单元读取的数据的静态锁存器，以及配置 存储对应于各种刷新周期的多个刷新模式选择代码，并且根据对应于所选择的刷新模式选择代码的刷新周期，通过在静态锁存器和动态锁存器之间交换数据来刷新动态锁存器。

公开(公告)号：US20120008424A1

公开(公告)日：2012-01-12

申请号：US13177642

申请日：2011-07-07

Applicant: Sang Oh LIM

Inventor： Sang Oh LIM

IPC: G11C7/10

CPC classification number: G11C7/12 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/26 ,  G11C2216/14

Abstract: A nonvolatile memory device includes a plurality of latches for storing data, a set/reset circuit for transferring data, stored in a selected latch of the latches, to a common node, a transmission circuit for transferring the data of the common node to a first sense node, a bit line transmission circuit for transferring the data of the first sense node to a bit line, a sense circuit for transferring the data of the first sense node to a second sense node, and a discharge circuit for changing a voltage level of the common node based on the data of the second sense node.

Abstract translation: 非易失性存储器件包括用于存储数据的多个锁存器，用于将存储在选定的锁存器的锁存器中的数据传送的设置/复位电路到公共节点，用于将公共节点的数据传送到第一 感测节点，用于将第一感测节点的数据传送到位线的位线传输电路，用于将第一感测节点的数据传送到第二感测节点的感测电路，以及用于改变第一感测节点的电压电平的放电电路 基于第二感知节点的数据的公共节点。

公开(公告)号：US20110280060A1

公开(公告)日：2011-11-17

申请号：US13191232

申请日：2011-07-26

Applicant: ROBERT NORMAN

Inventor： ROBERT NORMAN

IPC: G11C7/10 ,  G11C11/00

CPC classification number: G11C7/1096 ,  G11C5/02 ,  G11C7/1006 ,  G11C7/1078 ,  G11C7/1087 ,  G11C8/10 ,  G11C13/0033 ,  G11C13/004 ,  G11C13/0064 ,  G11C13/0069 ,  G11C16/10 ,  G11C16/26 ,  G11C16/3427 ,  G11C2013/0085 ,  G11C2013/0088 ,  G11C2213/71 ,  G11C2216/14

Abstract: Embodiments of the invention relate generally to data storage and computer memory, and more particularly, to systems, integrated circuits and methods for accessing memory in multiple layers of memory implementing, for example, third dimension memory technology. In a specific embodiment, an integrated circuit is configured to implement write buffers to access multiple layers of memory. For example, the integrated circuit can include memory cells disposed in multiple layers of memory. In one embodiment, the memory cells can be third dimension memory cells. The integrated circuit can also include read buffers that can be sized differently than the write buffers. In at least one embodiment, write buffers can be sized as a function of a write cycle. Each layer of memory can include a plurality of two-terminal memory elements that retain stored data in the absence of power and store data as a plurality of conductivity profiles.

Abstract translation: 本发明的实施例一般涉及数据存储和计算机存储器，更具体地，涉及用于访问实现例如第三维存储器技术的多层存储器中的存储器的系统，集成电路和方法。 在具体实施例中，集成电路被配置为实现写入缓冲器以访问多层存储器。 例如，集成电路可以包括设置在多层存储器中的存储单元。 在一个实施例中，存储器单元可以是第三维存储器单元。 集成电路还可以包括可以与写入缓冲器不同的读取缓冲器。 在至少一个实施例中，写入缓冲器的大小可以作为写周期的函数。 每层存储器可以包括多个两端存储元件，其在不存在功率的情况下保存存储的数据，并将数据存储为多个导电率分布。

公开(公告)号：US08050131B2

公开(公告)日：2011-11-01

申请号：US12534586

申请日：2009-08-03

Applicant: June Lee

Inventor： June Lee

IPC: G11C8/00

CPC classification number: G11C16/10 ,  G11C5/02 ,  G11C2216/14

Abstract: A system and method for performing memory operations in a multi-plane flash memory. Commands and addresses are sequentially provided to the memory for memory operations in memory planes. The memory operations are sequentially initiated and the memory operation for at least one of the memory planes is initiated during the memory operation for another memory plane. In one embodiment, each of a plurality of programming circuits is associated with a respective memory plane and is operable to program data to the respective memory plane in response to programming signals and when it is enabled. Control logic coupled to the plurality of programming circuits generates programming signals in response to the memory receiving program commands and further generates programming enable signals to individually enable each of the programming circuits to respond to the programming signals and stagger programming of data to each of the memory planes.

Abstract translation: 一种用于在多平面闪存中执行存储器操作的系统和方法。 命令和地址被顺序地提供给存储器以用于存储器平面中的存储器操作。 顺序地启动存储器操作，并且在另一存储器平面的存储器操作期间启动至少一个存储器平面的存储器操作。 在一个实施例中，多个编程电路中的每一个与相应的存储器平面相关联，并且可操作以响应于编程信号将数据编程到相应的存储器平面，并且当其被启用时。 耦合到多个编程电路的控制逻辑响应于存储器接收程序命令而产生编程信号，并进一步产生编程使能信号，以单独使编程电路中的每一个能够对编程信号做出响应，并将数据错开编程到每个存储器 飞机

公开(公告)号：US08050092B2

公开(公告)日：2011-11-01

申请号：US12474463

申请日：2009-05-29

Applicant: Chulmin Jung ,  Harry Hongyue Liu ,  Brian Lee ,  Yong Lu ,  Dadi Setiadi

Inventor： Chulmin Jung ,  Harry Hongyue Liu ,  Brian Lee ,  Yong Lu ,  Dadi Setiadi

IPC: G11C11/34 ,  G11C11/24

CPC classification number: G11C11/005 ,  G11C16/26 ,  G11C2216/14

Abstract: Method and apparatus for outputting data from a memory array having a plurality of non-volatile memory cells arranged into rows and columns. In accordance with various embodiments, charge is stored in a volatile memory cell connected to the memory array, and the stored charge is subsequently discharged from the volatile memory cell through a selected column. In some embodiments, the volatile memory cell is a dynamic random access memory (DRAM) cell from a row of the cells with each DRAM cell along the row coupled to a respective column in the memory array, and each column of non-volatile memory cells comprises Flash memory cells connected in a NAND configuration.

Abstract translation: 用于从具有排列成行和列的多个非易失性存储单元的存储器阵列输出数据的方法和装置。 根据各种实施例，电荷被存储在连接到存储器阵列的易失性存储单元中，并且随后通过所选择的列从易失性存储器单元中释放存储的电荷。 在一些实施例中，易失性存储器单元是来自单元行的动态随机存取存储器（DRAM）单元，每个DRAM单元沿着与存储器阵列中的相应列耦合的行，并且每列非易失性存储单元 包括以NAND配置连接的闪存单元。

公开(公告)号：US08006029B2

公开(公告)日：2011-08-23

申请号：US11607655

申请日：2006-11-30

Applicant: Ramkarthik Ganesan ,  Saad Monasa

Inventor： Ramkarthik Ganesan ,  Saad Monasa

IPC: G06F12/00

CPC classification number: G11C16/10 ,  G11C7/1039 ,  G11C7/1066 ,  G11C16/26 ,  G11C2216/14

Abstract: A Double Data Rate (DDR) nonvolatile memory for use with a wireless device. A host processor transfers commands and data through a DDR interface of the nonvolatile memory. The DDR nonvolatile memory implements legacy flash functions while maintaining DDR behavior.

Abstract translation: 用于无线设备的双数据速率（DDR）非易失性存储器。 主处理器通过非易失性存储器的DDR接口传送命令和数据。 DDR非易失性存储器在保持DDR行为的同时实现传统的闪存功能。

公开(公告)号：US07952924B2

公开(公告)日：2011-05-31

申请号：US12827892

申请日：2010-06-30

Applicant: Frankie F. Roohparvar ,  Ebrahim Abedifard

Inventor： Frankie F. Roohparvar ,  Ebrahim Abedifard

IPC: G11C11/34

CPC classification number: G11C16/0483 ,  G11C16/12 ,  G11C16/3459 ,  G11C2216/14

Abstract: A NAND Flash memory device is described that can reduce bit line coupling and floating gate coupling during program and verify operations. Consecutive bit lines of an array row are concurrently programmed as a common page. Floating gate coupling during programming can therefore be reduced. Multiple verify operations are performed on separate bit lines of the page. Bit line coupling can therefore be reduced.

Abstract translation: 描述了一种NAND闪存器件，其可以在编程和验证操作期间减少位线耦合和浮动栅极耦合。 阵列行的连续位线被同时编程为公共页面。 因此可以减少编程期间的浮动栅极耦合。 在页面的单独位线上执行多个验证操作。 因此可以减少位线耦合。

公开(公告)号：US07949821B2

公开(公告)日：2011-05-24

申请号：US12138137

申请日：2008-06-12

Applicant: Jin-Man Han

Inventor： Jin-Man Han

IPC: G06F13/00 ,  G06F13/28 ,  G11C11/34 ,  G11C16/04

CPC classification number: G11C16/10 ,  G11C8/08 ,  G11C16/3495 ,  G11C2216/14

Abstract: Methods and apparatus are disclosed, such as those involving a flash memory device. One such method includes storing data on memory cells on a memory block including a plurality of word lines and a plurality of memory cells on the word lines. The word lines comprising one or more bottom edge word lines, one or more top edge word lines, and intermediate word lines between the bottom and top edge word lines. The data is stored first on memory cells on the intermediate word lines. Then, a remaining portion, if any, of the data is stored on memory cells on the bottom edge word lines and/or the top edge word lines. This method enhances the life of the flash memory by preventing a premature failure of memory cells on the bottom or top edge word lines, which can be more prone to failure.

Abstract translation: 公开了诸如涉及闪存装置的方法和装置。 一种这样的方法包括将存储器单元上的数据存储在包括字线上的多个字线和多个存储器单元的存储器块上。 字线包括一个或多个底边字线，一个或多个顶边字线，以及底边和顶边字线之间的中间字线。 数据首先存储在中间字线上的存储单元上。 然后，数据的剩余部分（如果有的话）被存储在底部边缘字线和/或顶部边缘字线上的存储器单元上。 该方法通过防止底部或顶部边缘字线上的存储器单元的过早故障来增加闪存的寿命，这可能更容易发生故障。

公开(公告)号：US07944747B2

公开(公告)日：2011-05-17

申请号：US12400123

申请日：2009-03-09

Applicant: Dong-Hyuk Chae ,  Young-Ho Lim

Inventor： Dong-Hyuk Chae ,  Young-Ho Lim

IPC: G11C16/06

CPC classification number: G11C7/12 ,  G11C7/1006 ,  G11C16/04 ,  G11C16/10 ,  G11C29/50 ,  G11C2029/5006 ,  G11C2216/14

Abstract: Provided is a method for programming a flash memory device. The method includes receiving writing data, detecting leakage bit lines of the flash memory device, and updating the received writing data in order for data corresponding to the leakage bit lines to be modified as program-inhibit data. A programming operation is performed on the flash memory device after updating the writing data.

Abstract translation: 提供了一种用于对闪存设备进行编程的方法。 该方法包括接收写入数据，检测闪速存储器件的泄漏位线，以及更新所接收的写入数据，以便将与泄漏位线对应的数据修改为编程禁止数据。 在更新写入数据之后，对闪存设备执行编程操作。

公开(公告)号：US07940567B2

公开(公告)日：2011-05-10

申请号：US12191453

申请日：2008-08-14

Applicant: Seunghyun Moon ,  Kihwan Choi

Inventor： Seunghyun Moon ,  Kihwan Choi

IPC: G11C11/34

CPC classification number: G11C16/3404 ,  G11C16/0416 ,  G11C16/0483 ,  G11C16/10 ,  G11C2216/14 ,  H01L27/11524 ,  H01L27/11551 ,  H01L27/11578

Abstract: Example embodiments are directed to methods, memory devices, and systems for programming a nonvolatile memory device having a charge storage layer including performing at least one unit programming loop, each unit programming loop including, applying a programming pulse to at least two pages, applying a time delay to the at least two pages, and applying a verifying pulse to the at least two pages.

Abstract translation: 示例性实施例涉及用于编程具有电荷存储层的非易失性存储器件的方法，存储器件和系统，所述非易失性存储器件包括执行至少一个单元编程环路，每个单元编程回路包括将编程脉冲应用于至少两个页面， 至少两页的时间延迟，以及将验证脉冲施加到所述至少两个页面。