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公开(公告)号：US20230134063A1
公开(公告)日：2023-05-04
申请号：US17970351
申请日：2022-10-20
IPC分类号： H01L29/423 , H01L29/78
摘要： The present description concerns an electronic device comprising a semiconductor substrate, transistors having their gates contained in first trenches extending in the substrate, and at least one electronic component, different from a transistor, at least partly formed in a first semiconductor region contained in a second trench extending in the semiconductor substrate parallel to the first trenches.
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42.发明授权公开(公告)号：US11640972B2
公开(公告)日：2023-05-02
申请号：US17591233
申请日：2022-02-02
发明人： Abderrezak Marzaki
IPC分类号： H01L21/00 , H01L49/02 , H01L27/11521 , H01L27/11531 , H01L29/423 , H01L29/66 , H01L29/788
摘要： A semiconductor substrate has a front face with a first dielectric region. A capacitive element includes, on a surface of the first dielectric region at the front face, a stack of layers which include a first conductive region, a second conductive region and a third conductive region. The second conductive region is electrically insulated from the first conductive region by a second dielectric region. The second conductive region is further electrically insulated from the third conductive region by a third dielectric region. The first and third conductive regions form one plate of the capacitive element, and the second conductive region forms another plate of the capacitive element.
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公开(公告)号：US20230126011A1
公开(公告)日：2023-04-27
申请号：US18045097
申请日：2022-10-07
IPC分类号： G06T1/60 , G06F12/10 , G06F12/0802
摘要： In an embodiment a computer system includes at least one master module configured to process data having a format of N bits, a framebuffer configured to store pixel color component values of an image, the framebuffer having a resolution of N bits, each pixel being coded on P bits in the framebuffer and the pixels being stored one after another in the framebuffer and a memory management unit configured to control memory accesses of the at least one master module to the framebuffer, wherein the memory management unit is further configured to receive read memory access requests from the at least one master module, read at least one pixel in the framebuffer saved on P bits, and modify the format of the at least one read pixel by adding Q additional bits equal to a difference between N and P so as to format the at least one pixel on N bits before transmitting the at least one pixel to the at least one master module.
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公开(公告)号：US11637947B2
公开(公告)日：2023-04-25
申请号：US16669951
申请日：2019-10-31
发明人： Olivier Ferrand
摘要： A system includes an electronic module and an integrated circuit outside the electronic module. The integrated circuit is configured to generate a digital timing signal that emulates a first synchronization signal internal to the module and not available outside the module and to generate trigger signals based on the digital timing signal. A controller is configured to independently and autonomously perform control operations of the electronic module at times triggered by the trigger signals.
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公开(公告)号：US11621222B2
公开(公告)日：2023-04-04
申请号：US17173275
申请日：2021-02-11
发明人： Abderrezak Marzaki
IPC分类号： H01L29/66 , H01L23/522 , H01L21/762 , H01L27/08
摘要： A semiconductor region includes an isolating region which delimits a working area of the semiconductor region. A trench is located in the working area and further extends into the isolating region. The trench is filled by an electrically conductive central portion that is insulated from the working area by an isolating enclosure. A cover region is positioned to cover at least a first part of the filled trench, wherein the first part is located in the working area. A dielectric layer is in contact with the filled trench. A metal silicide layer is located at least on the electrically conductive central portion of a second part of the filled trench, wherein the second part is not covered by the cover region.
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公开(公告)号：US11621051B2
公开(公告)日：2023-04-04
申请号：US17647793
申请日：2022-01-12
摘要： A device includes a first switch, a first irreversibly programmable memory point, and a second irreversibly programmable memory point coupled in parallel with the first irreversibly programmable memory point. The first switch and the parallel combination of the first and second irreversibly programmable memory points are coupled in series between a first node and a second node.
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公开(公告)号：US11609851B2
公开(公告)日：2023-03-21
申请号：US17229161
申请日：2021-04-13
摘要： According to one aspect, a method for determining, for a memory allocation, placements in a memory area of data blocks generated by a neural network, comprises a development of an initial sequence of placements of blocks, each placement being selected from several possible placements, the initial sequence being defined as a candidate sequence, a development of at least one modified sequence of placements from a replacement of a given placement of the initial sequence by a memorized unselected placement, and, if the planned size of the memory area obtained by this modified sequence is less than that of the memory area of the candidate sequence, then this modified sequence becomes the candidate sequence, the placements of the blocks for the allocation being those of the placement sequence defined as a candidate sequence once each modified sequence has been developed.
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公开(公告)号：US11604082B2
公开(公告)日：2023-03-14
申请号：US17171726
申请日：2021-02-09
发明人： Laurent Beyly , Olivier Richard , Kenichi Oku
摘要： An embodiment of the present disclosure relates to a method of detection of a touch contact by a sensor including a first step of comparison of a voltage with a first voltage threshold; and a second step of comparison of the voltage with a second voltage threshold, the second step being implemented if the first voltage threshold has been reached within a duration shorter than a first duration threshold, the second voltage threshold being higher than the first voltage threshold.
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49.发明申请公开(公告)号：US20230075227A1
公开(公告)日：2023-03-09
申请号：US17898288
申请日：2022-08-29
申请人： STMICROELECTRONICS SA , STMICROELECTRONICS (ROUSSET) SAS , STMicroelectronics (Grand Ouest) SAS
IPC分类号： G06F9/445 , G06F3/0482
摘要： System, method, and circuitry for generating content for a programmable computing device based on user-selected configuration information. A settings registry is generated based on the user's selections. The settings registry and the user selected configuration information is utilized to generate the content, such as code, data, parameters, settings, etc. When the content is provided to the programmable computing device, the content initializes, configures, or controls one or more software and hardware aspects of the programmable computing device, such as boot sequence configurations, internal peripheral configurations, states of the programmable computing device, transitions between states of the programmable computing device, etc., and various combinations thereof.
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公开(公告)号：US11593289B2
公开(公告)日：2023-02-28
申请号：US16516988
申请日：2019-07-19
发明人： François Cloute , Sandrine Lendre
IPC分类号： G06F13/28
摘要： A memory contains a linked list of records representative of a plurality of data transfers via a direct memory access control circuit. Each record is representative of parameters of an associated data transfer of the plurality of data transfers. The parameters of each record include a transfer start condition of the associated data transfer and a transfer end event of the associated data transfer.
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