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公开(公告)号：US09148192B1
公开(公告)日：2015-09-29
申请号：US13962468
申请日：2013-08-08
Applicant: Xilinx, Inc.
Inventor： Alan C. Wong , Christopher J. Borrelli , Loren Jones , Seu Wah Low , Parag Upadhyaya , Robert M. Ondris , Sarosh I. Azad
IPC: H04B1/40
CPC classification number: H04L25/14
Abstract: An apparatus relating generally to a transmitter-side of a transceiver or a transmitter used to provide a clock signal is disclosed. In this apparatus, a first signal source is to provide a first periodic signal. A second signal source is to provide a second periodic signal. A first multiplexer is coupled to receive the first periodic signal and the second periodic signal to provide a selected one thereof as a first selected output. A phase interpolator is coupled to the first multiplexer to receive the first selected output. The phase interpolator includes a second multiplexer. The second multiplexer is coupled to receive the first selected output and a phase-interpolated version of the first selected output to output a selected one thereof as a second selected output. A divider is coupled to the second multiplexer to receive the second selected output to provide the clock signal.
Abstract translation: 公开了一种与用于提供时钟信号的收发机或发射机的发射机侧有关的装置。 在该装置中，第一信号源是提供第一周期信号。 第二信号源是提供第二周期信号。 第一多路复用器被耦合以接收第一周期性信号和第二周期信号，以将其选定的一个作为第一选择输出。 相位插值器耦合到第一多路复用器以接收第一选择的输出。 相位插值器包括第二多路复用器。 第二多路复用器被耦合以接收第一选择输出和第一选择输出的相位插值版本，以将其选定的一个输出作为第二选择输出。 分频器耦合到第二多路复用器以接收第二选择的输出以提供时钟信号。
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42.发明申请公开(公告)号：US20150061756A1
公开(公告)日：2015-03-05
申请号：US14014879
申请日：2013-08-30
Applicant: Xilinx, Inc.
Inventor： Aman Sewani , Parag Upadhyaya
IPC: H03K19/0185
CPC classification number: H03K19/018521 , H03K19/17744 , H03K19/1778 , H03K19/17788
Abstract: An input/output circuit implemented in an integrated circuit is described. The input/output circuit comprises an input/output pad and a voltage control circuit coupled to the input/output pad. The voltage control circuit sets a voltage at the input/output pad at a first voltage when the input/output pad is implemented as an input pad and at a second voltage when the input/output pad is implemented as an output pad. Methods of implementing input/output circuits in an integrated circuit are also described.
Abstract translation: 描述了在集成电路中实现的输入/输出电路。 输入/输出电路包括输入/输出焊盘和耦合到输入/输出焊盘的电压控制电路。 当输入/输出焊盘被实现为输入焊盘时，电压控制电路以第一电压设置输入/输出焊盘处的电压，并且当输入/输出焊盘被实现为输出焊盘时，电压控制电路将第二电压设置为第一电压。 还描述了在集成电路中实现输入/输出电路的方法。
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公开(公告)号：US20140117494A1
公开(公告)日：2014-05-01
申请号：US13661195
申请日：2012-10-26
Applicant: XILINX, INC.
Inventor： Jing Jing , Shuxian Wu , Parag Upadhyaya
IPC: H01L27/06
CPC classification number: H01L28/10 , H01F17/0013 , H01L23/5227 , H01L23/645 , H01L2924/0002 , H01L2924/00
Abstract: An inductor structure implemented within a semiconductor integrated circuit includes a coil of conductive material including at least one turn and a current return encompassing the coil. The current return is formed of a plurality of interconnected metal layers of the semiconductor integrated circuit.
Abstract translation: 在半导体集成电路内实现的电感器结构包括包括至少一个匝的导电材料的线圈和包围线圈的电流返回。 电流返回由半导体集成电路的多个互连的金属层形成。
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公开(公告)号：US11735519B2
公开(公告)日：2023-08-22
申请号：US17357087
申请日：2021-06-24
Applicant: XILINX, INC.
Inventor： Zhaoyin Daniel Wu , Parag Upadhyaya , Hong Shi
IPC: H01L23/522 , H01Q1/22
CPC classification number: H01L23/5227 , H01Q1/2283 , H01L2223/6672 , H01L2223/6677
Abstract: A package device comprises a first transceiver comprising a first integrated circuit (IC) die and transmitter circuitry, and a second transceiver comprising a second IC die and receiver circuitry. The receiver circuitry is coupled to the transmitter circuitry via a channel. The package device further comprises an interconnection device connected to the first IC die and the second IC die. The interconnection device comprises a channel connecting the transmitter circuitry with the receiver circuitry, and a passive inductive element disposed external to the first IC die and the second IC die and along the channel.
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公开(公告)号：US11728962B2
公开(公告)日：2023-08-15
申请号：US17644066
申请日：2021-12-13
Applicant: XILINX, INC.
Inventor： Shaojun Ma , Chi Fung Poon , Kevin Zheng , Parag Upadhyaya
CPC classification number: H04L7/0037 , H03K19/21
Abstract: Clock generation circuitry includes quadrature locked loop circuitry having first injection locked oscillator circuitry, second injection locked oscillator circuitry, and XOR circuitry. The first injection locked oscillator circuitry receives a first input signal and a second input signal and outputs first clock signals. The first input signal and the second input signal correspond to a reference clock signal. The second injection locked oscillator circuitry is coupled to outputs of the first injection locked oscillator circuitry, and receives the first clock signals and generates second clock signals. The XOR circuitry receives the second clock signals and generates a first clock signal, a second clock signal, a third clock signal, and a fourth clock signal. The frequencies of the first clock signal, the second clock signal, the third clock signal, and the fourth clock signal are greater than the frequency of the reference clock signal.
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Patent Agency Ranking
公开(公告)号：US11575497B2
公开(公告)日：2023-02-07
申请号：US17351028
申请日：2021-06-17
Applicant: XILINX, INC.
Inventor： Wenfeng Zhang , Zhaoyin Daniel Wu , Parag Upadhyaya
Abstract: In one example, receiver circuitry for a communication system comprises signal processing circuitry configured to receive a data signal and generate a processed data signal, and error slicer circuitry. The error slicer circuitry is coupled to the output of the signal processing circuitry, and configured to receive the processed data signal. The error slicer circuitry comprises a first error slicer configured to receive a clock signal, and output a first error signal based on a first state of the clock signal and processed data signal. The first error slicer is further configured to output a second error signal based on a second state of the clock signal and the processed data signal.
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公开(公告)号：US11469877B1
公开(公告)日：2022-10-11
申请号：US17400762
申请日：2021-08-12
Applicant: XILINX, INC.
Inventor： Mayank Raj , Parag Upadhyaya
Abstract: Some examples described herein provide an integrated circuit comprising an auxiliary clock and data recovery (CDR) circuitry. The CDR circuitry is configured to oversample an incoming data signal and generate a locked clock signal. The auxiliary CDR circuitry may comprise a phase-locked loop (PLL) configured to receive the incoming data signal and generate the locked clock signal. The PLL may comprise a phase detector (PD) configured to receive the incoming data signal and capture a number of samples of the incoming data signal in response to a number of adjacent clock signals and minimum data transition thresholds implemented by an intersymbol interference (ISI) filter, the minimum data transition thresholds identifying minimum data transitions in the incoming data signal.
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公开(公告)号：US11005572B1
公开(公告)日：2021-05-11
申请号：US17093399
申请日：2020-11-09
Applicant: XILINX, INC.
Inventor： Ping Chuan Chiang , Mayank Raj , Chuan Xie , Stanley Y. Chen , Sandeep Kumar , Sukruth Pattanagiri , Parag Upadhyaya , Yohan Frans
Abstract: Examples described herein generally relate to a temperature-locked loop for optical elements. In an example, a device includes a controller and a digital-to-analog converter (DAC). The controller includes a DC-controllable transimpedance stage (DCTS), a slicer circuit, and a processor. The DCTS is configured to be coupled to a photodiode. An input node of the slicer circuit is coupled to an output node of the DCTS. The processor has an input node coupled to an output node of the slicer circuit. The DAC has an input node coupled to an output node of the processor and is configured to be coupled to a heater. The processor is configured to control (i) the DCTS to reduce a DC component of a signal on the output node of the DCTS and (ii) an output voltage on the output node of the DAC, both based on a signal output by the slicer circuit.
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公开(公告)号：US11003203B2
公开(公告)日：2021-05-11
申请号：US16518365
申请日：2019-07-22
Applicant: Xilinx, Inc.
Inventor： Chi Fung Poon , Asma Laraba , Parag Upadhyaya
Abstract: A circuit arrangement for calibrating a circuit in an integrated circuit device is described. The circuit arrangement may comprise a main circuit configured to receive input data at a first input and generate output data at a first output, wherein the output data is based upon the input data and a function of the main circuit; a replica circuit configured to receive calibration data at a second input and generate calibration output data, based upon the calibration data, at a second output, wherein the replica circuit provides a replica function of the function of the main circuit; and a calibration circuit configured to receive the output data from the main circuit during a foreground calibration mode, and the calibration output data from the replica circuit during a background calibration mode; wherein the calibration circuit provides control signals to the main circuit during the background calibration mode. A method of calibrating a circuit in an integrated circuit device is also described.
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公开(公告)号：US20200293080A1
公开(公告)日：2020-09-17
申请号：US16518365
申请日：2019-07-22
Applicant: Xilinx, Inc.
Inventor： Chi Fung Poon , Asma Laraba , Parag Upadhyaya
Abstract: A circuit arrangement for calibrating a circuit in an integrated circuit device is described. The circuit arrangement may comprise a main circuit configured to receive input data at a first input and generate output data at a first output, wherein the output data is based upon the input data and a function of the main circuit; a replica circuit configured to receive calibration data at a second input and generate calibration output data, based upon the calibration data, at a second output, wherein the replica circuit provides a replica function of the function of the main circuit; and a calibration circuit configured to receive the output data from the main circuit during a foreground calibration mode, and the calibration output data from the replica circuit during a background calibration mode; wherein the calibration circuit provides control signals to the main circuit during the background calibration mode. A method of calibrating a circuit in an integrated circuit device is also described.
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