Abstract:
A circuit for generating a divided clock signal with a configurable phase offset comprises a first latch circuit adapted to receive a clock signal to be divided; a second latch coupled to an output of the first latch circuit and generating a divided output clock signal; and an initialization circuit coupled to the first latch circuit and the second latch circuit, the initialization circuit coupled to receive an initialization signal. The initialization signal determines a phase offset between the divided output clock signal and the clock signal to be divided. A method of generating a divided clock signal is also described.
Abstract:
An input/output circuit implemented in an integrated circuit is described. The input/output circuit comprises an input/output pad and a voltage control circuit coupled to the input/output pad. The voltage control circuit sets a voltage at the input/output pad at a first voltage when the input/output pad is implemented as an input pad and at a second voltage when the input/output pad is implemented as an output pad. Methods of implementing input/output circuits in an integrated circuit are also described.
Abstract:
An input/output circuit implemented in an integrated circuit is described. The input/output circuit comprises an input/output pad and a voltage control circuit coupled to the input/output pad. The voltage control circuit sets a voltage at the input/output pad at a first voltage when the input/output pad is implemented as an input pad and at a second voltage when the input/output pad is implemented as an output pad. Methods of implementing input/output circuits in an integrated circuit are also described.