公开(公告)号：US09237041B1

公开(公告)日：2016-01-12

申请号：US14601587

申请日：2015-01-21

Applicant: Xilinx, Inc.

Inventor： Fu-Tai An ,  Didem Z. Turker Melek ,  Yuan-Shih Chen

IPC: H04L27/18 ,  H04L25/03 ,  H04L7/00 ,  H04L1/00 ,  H04L25/02

CPC classification number: H04L25/03057 ,  H04L1/0002 ,  H04L7/0025 ,  H04L7/0058 ,  H04L25/0292 ,  H04L25/03146 ,  H04L25/03885 ,  H04L2025/0349

Abstract: A method relates generally to data reception for any of a plurality of data rates. In such a method, information and phases of a clock signal are obtained by a decision feedback equalizer. The information is equalized using the phases of the clock signal with the decision feedback equalizer to provide equalized sample streams. The equalized sample streams and the phases of the clock signal are provided to a selection circuit block. A first and a second phase of the phases are swapped, along with swapping a first and a second equalized sample stream corresponding to the first phase and the second phase, responsive to a data rate of the plurality of data rates.

Abstract translation: 一种方法一般涉及多种数据速率中的任一种的数据接收。 在这种方法中，通过判决反馈均衡器获得时钟信号的信息和相位。 使用具有判决反馈均衡器的时钟信号的相位来均衡信息以提供均衡的采样流。 均衡采样流和时钟信号的相位被提供给选择电路块。 交换相的第一和第二阶段，以及响应于多个数据速率的数据速率交换对应于第一相位和第二阶段的第一和第二均衡采样流。

公开(公告)号：US09553592B1

公开(公告)日：2017-01-24

申请号：US14639197

申请日：2015-03-05

Applicant: Xilinx, Inc.

Inventor： Aman Sewani ,  Fu-Tai An ,  Parag Upadhyaya

IPC: H03K21/00 ,  H03K23/00 ,  H03K25/00 ,  H03K21/02 ,  H03K5/13

CPC classification number: H03K21/02 ,  H03K5/13

Abstract: A circuit for generating a divided clock signal with a configurable phase offset comprises a first latch circuit adapted to receive a clock signal to be divided; a second latch coupled to an output of the first latch circuit and generating a divided output clock signal; and an initialization circuit coupled to the first latch circuit and the second latch circuit, the initialization circuit coupled to receive an initialization signal. The initialization signal determines a phase offset between the divided output clock signal and the clock signal to be divided. A method of generating a divided clock signal is also described.

Abstract translation: 用于产生具有可配置相位偏移的分频时钟信号的电路包括适于接收待分频的时钟信号的第一锁存电路; 第二锁存器，耦合到所述第一锁存电路的输出并产生分频的输出时钟信号; 以及耦合到所述第一锁存电路和所述第二锁存电路的初始化电路，所述初始化电路被耦合以接收初始化信号。 初始化信号决定分割后的输出时钟信号与待分割的时钟信号之间的相位偏移。 还描述了产生分频时钟信号的方法。