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41.发明授权公开(公告)号：US08619463B2
公开(公告)日：2013-12-31
申请号：US13676389
申请日：2012-11-14
Inventor： Hank Cheng , Ming-Zhang Kuo , Chung-Cheng Chou
CPC classification number: G11C7/00 , G11C7/20 , G11C8/08 , G11C11/413 , G11C2207/2254
Abstract: A memory including a capacitor coupled to a write bit line or a word line and an initializer configured to initialize a voltage level at a first node between the capacitor and the write bit line or the word line. The memory further includes a controllable initial level adjuster configured to adjust a voltage level of a second node at one terminal of the capacitor in response to a pulse. The capacitor is configured to receive a boost signal at a third node at a terminal opposite the first node. The boost signal configured to change a voltage level of the write bit line or the word line in response to the boost signal.
Abstract translation: 包括耦合到写位线或字线的电容器的存储器和被配置为初始化电容器和写位线或字线之间的第一节点处的电压电平的初始化器。 存储器还包括可控的初始电平调节器，其被配置为响应于脉冲调节电容器的一个端子处的第二节点的电压电平。 电容器被配置为在与第一节点相对的端子处的第三节点处接收升压信号。 升压信号被配置为响应于升压信号改变写位线或字线的电压电平。
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公开(公告)号：US12248331B2
公开(公告)日：2025-03-11
申请号：US17877115
申请日：2022-07-29
Inventor： Zheng-Jun Lin , Chung-Cheng Chou , Yu-Der Chih , Chin-I Su
Abstract: A voltage regulator circuit is provided. The voltage regulator circuit includes a voltage regulator configured to provide an output voltage at an output terminal. A plurality of macros are connectable at a plurality of connection nodes of a connector connected to the output terminal of the voltage regulator. A feedback circuit having a plurality of feedback loops is connectable to the plurality of connection nodes. The feedback loop of the plurality of feedback loops, when connected to a connection node of the plurality of connection nodes, is configured to provide an instantaneous voltage of the connection node as a feedback to the voltage regulator. The voltage regulator is configured, in response to the instantaneous voltage, regulate the output voltage to maintain the instantaneous voltage of the connection node approximately equal to a reference voltage.
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公开(公告)号：US12218585B2
公开(公告)日：2025-02-04
申请号：US18230450
申请日：2023-08-04
Inventor： Chung-Cheng Chou , Tien-Yen Wang
Abstract: A system includes a charge pump system having a plurality of enable signal input terminals and an output terminal, the charge pump system configured to provide an output voltage at the output terminal; and a detection circuit connected to the enable terminals and the output terminal of the charge pump system, the detection circuit configured to compare the charge pump system output voltage to a plurality of predefined input detection voltage levels, and to selectively output a plurality of enable signals to the charge pump system enable signal input terminals in response to the comparison.
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公开(公告)号：US11984162B2
公开(公告)日：2024-05-14
申请号：US17981977
申请日：2022-11-07
Inventor： Zheng-Jun Lin , Chung-Cheng Chou , Yu-Der Chih , Pei-Ling Tseng
CPC classification number: G11C13/0064 , G11C13/003 , G11C13/004
Abstract: The disclosed invention presents a self-tracking reference circuit that compensates for IR drops and achieves the target resistance state at different temperatures after write operations. The disclosed self-tracking reference circuit includes a replica access path, a configurable resistor network, a replica selector mini-array and a step current generator that track PVT variations to provide a PVT tracking level for RRAM verify operation.
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公开(公告)号：US20240036597A1
公开(公告)日：2024-02-01
申请号：US17877115
申请日：2022-07-29
Inventor： Zheng-Jun Lin , Chung-Cheng Chou , Yu-Der Chih , Chin-I Su
Abstract: A voltage regulator circuit is provided. The voltage regulator circuit includes a voltage regulator configured to provide an output voltage at an output terminal. A plurality of macros are connectable at a plurality of connection nodes of a connector connected to the output terminal of the voltage regulator. A feedback circuit having a plurality of feedback loops is connectable to the plurality of connection nodes. The feedback loop of the plurality of feedback loops, when connected to a connection node of the plurality of connection nodes, is configured to provide an instantaneous voltage of the connection node as a feedback to the voltage regulator. The voltage regulator is configured, in response to the instantaneous voltage, regulate the output voltage to maintain the instantaneous voltage of the connection node approximately equal to a reference voltage.
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Patent Agency Ranking
公开(公告)号：US20230396161A1
公开(公告)日：2023-12-07
申请号：US18230450
申请日：2023-08-04
Inventor： Chung-Cheng Chou , Tien-Yen Wang
CPC classification number: H02M3/07 , G11C13/0038 , G11C5/145
Abstract: A system includes a charge pump system having a plurality of enable signal input terminals and an output terminal, the charge pump system configured to provide an output voltage at the output terminal; and a detection circuit connected to the enable terminals and the output terminal of the charge pump system, the detection circuit configured to compare the charge pump system output voltage to a plurality of predefined input detection voltage levels, and to selectively output a plurality of enable signals to the charge pump system enable signal input terminals in response to the comparison.
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公开(公告)号：US20230317159A1
公开(公告)日：2023-10-05
申请号：US17709662
申请日：2022-03-31
Inventor： Yu-Der Chih , Chung-Cheng Chou , Chun-Yun Wu , Chen-Ming Hung
IPC: G11C13/00
CPC classification number: G11C13/0069 , G11C13/0064 , G11C13/004 , G11C13/0028 , G11C13/0026 , G11C13/0038
Abstract: A memory device includes a main array comprising main memory cells; a redundancy array comprising redundancy memory cells; and write circuitry configured to perform a first programming operation on a main memory cell, to detect whether a current of the main memory cell exceeds a predefined current threshold during the first programming operation, and to disable a second programming operation for a redundancy memory cell if the current of the main memory cell exceeds the predefined current threshold during the first programming operation.
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公开(公告)号：US11735263B2
公开(公告)日：2023-08-22
申请号：US17871144
申请日：2022-07-22
Inventor： Chin-I Su , Chung-Cheng Chou , Yu-Der Chih , Zheng-Jun Lin
IPC: G11C13/00
CPC classification number: G11C13/0069 , G11C13/0028 , G11C13/0038 , G11C2013/0078 , G11C2213/79
Abstract: A method of operating a memory circuit includes generating a first voltage by a first amplifier circuit of a first driver circuit coupled to a first column of memory cells, and generating a first current in response to the first voltage. The first current includes a first set of leakage currents and a first write current. The method further includes generating, by a tracking circuit, a second set of leakage currents configured to track the first set of leakage currents of the first column of memory cells, and mirroring the first current in a first path with a second current in a second path by a first current mirror. The second current includes the second set of leakage currents and a second write current. The first write current corresponds to the second write current. The first set of leakage currents corresponds to the second set of leakage currents.
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公开(公告)号：US11609815B1
公开(公告)日：2023-03-21
申请号：US17461532
申请日：2021-08-30
Inventor： Zheng-Jun Lin , Pei-Ling Tseng , Hsueh-Chih Yang , Chung-Cheng Chou , Yu-Der Chih
Abstract: A semiconductor device includes a memory circuit, an error correction code circuit, a register circuit and a write circuit. The memory circuit is configured to output, in response to at least one address signal, first data associated with at least one memory cell in the memory circuit. The error correction code circuit is configured to convert the first data to second data and configured to generate error information when the first data is not identical to the second data. The register circuit is configured to output, based on the error information, reset information corresponding to the at least one address signal. The write circuit is configured to reset the at least one memory cell according to the reset information. A method is also disclosed herein.
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公开(公告)号：US11495294B2
公开(公告)日：2022-11-08
申请号：US17106725
申请日：2020-11-30
Inventor： Zheng-Jun Lin , Chung-Cheng Chou , Yu-Der Chih , Pei-Ling Tseng
Abstract: The disclosed invention presents a self-tracking reference circuit that compensates for IR drops and achieves the target resistance state at different temperatures after write operations. The disclosed self-tracking reference circuit includes a replica access path, a configurable resistor network, a replica selector mini-array and a step current generator that track PVT variations to provide a PVT tracking level for RRAM verify operation.
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