METHOD AND DEVICE FOR MANAGING MEMORY OF USER DEVICE
    41.
    发明申请
    METHOD AND DEVICE FOR MANAGING MEMORY OF USER DEVICE 审中-公开
    用于管理用户设备的存储器的方法和设备

    公开(公告)号:US20170031721A1

    公开(公告)日:2017-02-02

    申请号:US15289940

    申请日:2016-10-10

    CPC classification number: G06F9/5022 G06F9/485

    Abstract: A method and a device dynamically managing background processes according to a memory status so as to efficiently use the memory in a user device supporting a multitasking operating system. The method includes determining reference information for adjustment of the number of background processes; identifying a memory status based on the reference information; and adjusting the number of the background processes in correspondence to the memory status.

    Abstract translation: 一种方法和设备,其根据存储器状态动态地管理后台进程,以便有效地使用支持多任​​务操作系统的用户设备中的存储器。 该方法包括确定用于调整后台进程数量的参考信息; 基于参考信息识别存储器状态; 以及根据存储器状态调整后台进程的数量。

    Method and device for managing memory of user device
    42.
    发明授权
    Method and device for managing memory of user device 有权
    用于管理用户设备的存储器的方法和设备

    公开(公告)号:US09465661B2

    公开(公告)日:2016-10-11

    申请号:US14261289

    申请日:2014-04-24

    CPC classification number: G06F9/5022 G06F9/485

    Abstract: A method and a device dynamically managing background processes according to a memory status so as to efficiently use the memory in a user device supporting a multitasking operating system.The method includes determining reference information for adjustment of the number of background processes; identifying a memory status based on the reference information; and adjusting the number of the background processes in correspondence to the memory status.

    Abstract translation: 该方法包括确定用于调整后台进程数量的参考信息; 基于参考信息识别存储器状态; 以及根据存储器状态调整后台进程的数量。

    Semiconductor package including semiconductor chips stacked via conductive bumps

    公开(公告)号:US12272661B2

    公开(公告)日:2025-04-08

    申请号:US17564689

    申请日:2021-12-29

    Abstract: A semiconductor package includes a first semiconductor chip including a first bonding pad on a first surface of a first substrate, a first through electrode penetrating through the first substrate and electrically connected to the first bonding pad, a first recess with a desired depth in the first substrate from a second surface of the first substrate and exposing an end portion of the first through electrode, and a second bonding pad in the first recess and electrically connected to the first through electrode, a second semiconductor chip stacked on the second surface of the first substrate and including a third bonding pad on a third surface of a second substrate, and a conductive connection member between the second bonding pad and the third bonding pad. At least a portion of the conductive connection member may be in the first recess.

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