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公开(公告)号:US11967962B2
公开(公告)日:2024-04-23
申请号:US17860519
申请日:2022-07-08
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Jusung Lee , Wooseok Kim , Wonsik Yu , Chanyoung Jeong
CPC classification number: H03L7/0991 , H03L7/07 , H03L7/091 , H03L7/18
Abstract: A frequency-locked loop (FLL) logic circuit, including a validity signal generator configured to receive an external clock signal and determine whether a glitch occurs in the external clock signal; a clock divider configured to generate a reference frequency clock signal based on the external clock signal and a determination result of the validity signal generator; a synchronizer configured to synchronize a phase of an oscillator clock signal with a phase of the reference frequency clock signal; a clock counter configured to count a number of pulses of the oscillator clock signal during a reference time; and a code limiter configured to determine a range of a frequency selection value for calibrating an operating frequency of the oscillator clock signal based on the counted number of pulses.
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公开(公告)号:US11789482B2
公开(公告)日:2023-10-17
申请号:US17702482
申请日:2022-03-23
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Jusung Lee , Wooseok Kim , Taeik Kim , Chanyoung Jeong
Abstract: A bandgap reference circuit includes a reference current generation circuit configured to output a bandgap reference current insensitive to a temperature change, by using a first voltage inversely proportional to temperature and a third voltage proportional to temperature. The third voltage is a difference between the first voltage and a second voltage. The bandgap reference circuit further includes a resistivity temperature coefficient cancellation circuit configured to remove a first current proportional to temperature from the bandgap reference current by using the third voltage, and a reference voltage generation circuit configured to output a bandgap reference voltage insensitive to a temperature change by using a second current inversely proportional to temperature and a first resistance proportional to temperature. The second current is generated by removing the first current from the bandgap reference current.
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公开(公告)号:US11824663B2
公开(公告)日:2023-11-21
申请号:US17519818
申请日:2021-11-05
Applicant: Samsung Electronics Co., Ltd.
Inventor: Dongho Kim , Jongmin Baik , Jusung Lee
IPC: H04L1/1829 , H04L1/1812 , H04B17/309 , H04L1/1867 , H04W72/21
CPC classification number: H04L1/1854 , H04B17/309 , H04L1/1812 , H04L1/1835 , H04L1/1848 , H04L1/1874 , H04W72/21
Abstract: Various embodiments of the disclosure relate to an apparatus and a method for managing a communication buffer of an electronic device in the electronic device. The electronic device includes: a wireless communication circuit, an application processor, and a communication processor operatively connected to the wireless communication circuit and the application processor and including a communication buffer, wherein the communication processor is configured to: identify a Radio Link Control (RLC) retransmission time, identify an uplink transmission rate, and configure a size of an area for storing data in the communication buffer based on the RLC retransmission time and the uplink transmission rate.
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