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    METHODS OF MAKING THREE DIMENSIONAL NAND DEVICES
    43.
    发明申请
    METHODS OF MAKING THREE DIMENSIONAL NAND DEVICES 有权
    制造三维NAND器件的方法

    公开(公告)号：US20150380423A1

    公开(公告)日：2015-12-31

    申请号：US14319283

    申请日：2014-06-30

    申请人： SanDisk Technologies, Inc.

    发明人： Senaka Krishna Kanakamedala ,  Yanli Zhang ,  Raghuveer S. Makala ,  Yao-Sheng Lee ,  Johann Alsmeier ,  George Matamis

    IPC分类号： H01L27/115 ,  H01L21/3213 ,  H01L21/311 ,  H01L29/49 ,  H01L21/02 ,  H01L21/28

    CPC分类号： H01L27/11556 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02271 ,  H01L21/02274 ,  H01L21/28273 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/32133 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11526 ,  H01L29/4916

    摘要： A method of making a monolithic three dimensional NAND string includes providing a first stack of alternating first material layers and second material layers over a major surface of a substrate. The first material layers include first silicon oxide layers, the second material layers include second silicon oxide layers, and the first silicon oxide layers have a different etch rate from the second silicon oxide when exposed to the same etching medium. The first stack includes a back side opening, a front side opening, and at least a portion of a floating gate layer, a tunnel dielectric and a semiconductor channel located in the front side opening. The method also includes selectively removing the first material layers through the back side opening to form back side control gate recesses between adjacent second material layers.

    摘要翻译： 制造单片三维NAND串的方法包括在衬底的主表面上提供交替的第一材料层和第二材料层的第一堆叠。 第一材料层包括第一氧化硅层，第二材料层包括第二氧化硅层，并且当暴露于相同的蚀刻介质时，第一氧化硅层具有与第二氧化硅不同的蚀刻速率。 第一堆叠包括背侧开口，前侧开口，以及至少一部分浮栅层，隧道电介质和位于前侧开口中的半导体通道。 该方法还包括通过后侧开口选择性地去除第一材料层，以在相邻的第二材料层之间形成背侧控制栅极凹部。

    MULTI-LEVEL CONTACT TO A 3D MEMORY ARRAY AND METHOD OF MAKING
    44.
    发明申请
    MULTI-LEVEL CONTACT TO A 3D MEMORY ARRAY AND METHOD OF MAKING 有权
    多层联系3D内存阵列及制作方法

    公开(公告)号：US20150179663A1

    公开(公告)日：2015-06-25

    申请号：US14631047

    申请日：2015-02-25

    申请人： SANDISK TECHNOLOGIES INC.

    发明人： Yao-Sheng Lee ,  Zhen Chen ,  Syo Fukata

    IPC分类号： H01L27/115

    CPC分类号： H01L27/11578 ,  H01L21/76816 ,  H01L21/76829 ,  H01L23/481 ,  H01L27/10802 ,  H01L27/11 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11548 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11568 ,  H01L27/1157 ,  H01L27/11575 ,  H01L27/11582 ,  H01L29/66 ,  H01L29/7926 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A method of making multi-level contacts. The method includes providing an in-process multilevel device including at least one device region and at least one contact region. The contact region includes a plurality of electrically conductive layers configured in a step pattern. The method also includes forming a conformal etch stop layer over the plurality of electrically conductive layers, forming a first electrically insulating layer over the etch stop layer, forming a conformal sacrificial layer over the first electrically insulating layer and forming a second electrically insulating layer over the sacrificial layer. The method also includes etching a plurality of contact openings through the etch stop layer, the first electrically insulating layer, the sacrificial layer and the second electrically insulating layer in the contact region to the plurality of electrically conductive layers.

    摘要翻译： 制作多层次联系的方法。 该方法包括提供包括至少一个设备区域和至少一个接触区域的进程内多电平设备。 接触区域包括以台阶图案配置的多个导电层。 该方法还包括在多个导电层上形成共形蚀刻停止层，在蚀刻停止层上形成第一电绝缘层，在第一电绝缘层上形成共形牺牲层，并形成第二电绝缘层 牺牲层。 该方法还包括通过蚀刻停止层，接触区域中的第一电绝缘层，牺牲层和第二电绝缘层蚀刻到多个导电层的多个接触开口。

    METHOD OF MAKING A VERTICAL NAND DEVICE USING SEQUENTIAL ETCHING OF MULTILAYER STACKS
    45.
    发明申请
    METHOD OF MAKING A VERTICAL NAND DEVICE USING SEQUENTIAL ETCHING OF MULTILAYER STACKS 有权
    使用多层堆叠的顺序蚀刻制造垂直NAND器件的方法

    公开(公告)号：US20150118811A1

    公开(公告)日：2015-04-30

    申请号：US14585912

    申请日：2014-12-30

    申请人： SANDISK TECHNOLOGIES INC.

    发明人： Raghuveer S. Makala ,  Yao-Sheng Lee ,  Jayavel Pachamuthu ,  Johann Alsmeier ,  Henry Chien

    IPC分类号： H01L27/115

    CPC分类号： H01L27/11582 ,  H01L21/822 ,  H01L21/8221 ,  H01L27/0688 ,  H01L27/11519 ,  H01L27/11556 ,  H01L27/11565 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7889 ,  H01L29/7926

    摘要： A method of making a vertical NAND device includes forming a lower portion of a memory stack over a substrate, forming a lower portion of memory openings in the lower portion of the memory stack, and at least partially filling the lower portion of the memory openings with a sacrificial material. The method also includes forming an upper portion of the memory stack over the lower portion of the memory stack and over the sacrificial material, forming an upper portion of the memory openings in the upper portion of the memory stack to expose the sacrificial material in the lower portion of the memory openings, removing the sacrificial material to connect the lower portion of the memory openings with a respective upper portion of the memory openings to form continuous memory openings, and forming a semiconductor channel in each continuous memory opening.

    摘要翻译： 制造垂直NAND器件的方法包括在衬底上形成存储器堆叠的下部，在存储堆的下部形成存储器开口的下部，并至少部分地填充存储器开口的下部， 牺牲材料。 该方法还包括在存储器堆叠的下部并在牺牲材料的上方形成存储器堆叠的上部，在存储器堆叠的上部形成存储器开口的上部部分，以将下部的牺牲材料露出 部分存储器开口，去除牺牲材料以将存储器开口的下部与存储器开口的相应上部连接以形成连续的存储器开口，并在每个连续的存储器开口中形成半导体通道。

    HIGH ASPECT RATIO MEMORY HOLE CHANNEL CONTACT FORMATION
    46.
    发明申请
    HIGH ASPECT RATIO MEMORY HOLE CHANNEL CONTACT FORMATION 有权
    高比例记忆孔通道接触形成

    公开(公告)号：US20150079765A1

    公开(公告)日：2015-03-19

    申请号：US14225116

    申请日：2014-03-25

    申请人： SanDisk Technologies, Inc.

    发明人： Jayavel Pachamuthu ,  Johann Alsmeier ,  Raghuveer S. Makala ,  Yao-Sheng Lee

    IPC分类号： H01L21/28

    CPC分类号： H01L21/28282 ,  H01L21/28273 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11582 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7889 ,  H01L29/7926

    摘要： A method of fabricating a semiconductor device, such as a three-dimensional monolithic NAND memory string, includes etching a select gate electrode over a first gate insulating layer over a substrate to form an opening, forming a second gate insulating layer over the sidewalls of the opening, forming a sacrificial spacer layer over the second gate insulating layer on the sidewalls of the opening, and etching the first gate insulating layer over the bottom surface of the opening to expose the substrate, removing the sacrificial spacer layer to expose the second gate insulating layer over the sidewalls of the opening, and forming a protrusion comprising a semiconductor material within the opening and contacting the substrate, wherein the second gate insulating layer is located between the select gate electrode and first and second side surfaces of the protrusion.

    摘要翻译： 一种制造诸如三维单片NAND存储器串的半导体器件的方法包括在衬底上的第一栅极绝缘层上蚀刻选择栅电极以形成开口，在所述第二栅极绝缘层的侧壁上形成第二栅极绝缘层 开口，在开口的侧壁上的第二栅极绝缘层上形成牺牲间隔层，并且在开口的底表面上蚀刻第一栅极绝缘层以暴露衬底，去除牺牲间隔层以暴露第二栅极绝缘 在开口的侧壁上方形成包括半导体材料在内的突起并与衬底接触的突起，其中第二栅极绝缘层位于选择栅电极与突起的第一和第二侧表面之间。

    METHODS OF FABRICATING A THREE-DIMENSIONAL NON-VOLATILE MEMORY DEVICE
    47.
    发明申请
    METHODS OF FABRICATING A THREE-DIMENSIONAL NON-VOLATILE MEMORY DEVICE 有权
    制造三维非易失性存储器件的方法

    公开(公告)号：US20150079743A1

    公开(公告)日：2015-03-19

    申请号：US14264312

    申请日：2014-04-29

    申请人： SanDisk Technologies, Inc.

    发明人： Jayavel Pachamuthu ,  Johann Alsmeier ,  Raghuveer S. Makala ,  Yao-Sheng Lee

    IPC分类号： H01L27/115

    CPC分类号： H01L27/11551 ,  H01L21/022 ,  H01L21/30604 ,  H01L27/0688 ,  H01L27/101 ,  H01L27/1052 ,  H01L27/1128 ,  H01L27/11556 ,  H01L27/11578 ,  H01L27/11582 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7926

    摘要： A method of fabricating a memory device, such as a three-dimensional NAND string, includes forming a trench through a stack of alternating first and second material layers to expose a source region of a semiconductor channel, partially filling the trench with a protective material, removing at least a portion of the alternating second material layers to form recesses between the first material layers, forming a conductive material in the recesses to form control gate electrodes for a memory device, depositing an insulating material over the sidewalls and bottom of the trench, etching through the insulating material and the protective material to expose the semiconductor channel at the trench bottom while leaving the insulating material on the trench sidewalls, and filling the trench with a source line that electrically contacts the source region while the insulating material is between the source line and the control gate electrodes along the trench sidewalls.

    摘要翻译： 一种制造诸如三维NAND串的存储器件的方法包括通过交替的第一和第二材料层的堆叠形成沟槽，以暴露半导体沟道的源极区域，用保护材料部分地填充沟槽， 去除所述交替的第二材料层的至少一部分以在所述第一材料层之间形成凹陷，在所述凹部中形成导电材料以形成用于存储器件的控制栅电极，在所述沟槽的侧壁和底部上沉积绝缘材料， 通过绝缘材料和保护材料蚀刻，以在沟槽底部露出半导体沟道，同时将绝缘材料留在沟槽侧壁上，并且用沟槽源填充沟槽，源极线与源极区域电接触，而绝缘材料位于源极之间 线和沿着沟槽侧壁的控制栅电极。

    Method of Making a Three-Dimensional Memory Array with Etch Stop
    48.
    发明申请
    Method of Making a Three-Dimensional Memory Array with Etch Stop 有权
    制造具有蚀刻停止的三维存储器阵列的方法

    公开(公告)号：US20140054670A1

    公开(公告)日：2014-02-27

    申请号：US14066788

    申请日：2013-10-30

    申请人： SanDisk Technologies, Inc.

    发明人： Yao-Sheng Lee ,  Johann Alsmeier

    IPC分类号： H01L27/115

    CPC分类号： H01L27/11551 ,  H01L21/764 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11578 ,  H01L27/11582 ,  H01L29/7889 ,  H01L29/7926

    摘要： A three dimensional memory device including a substrate and a semiconductor channel. At least one end portion of the semiconductor channel extends substantially perpendicular to a major surface of the substrate. The device also includes at least one charge storage region located adjacent to semiconductor channel and a plurality of control gate electrodes having a strip shape extending substantially parallel to the major surface of the substrate. The plurality of control gate electrodes include at least a first control gate electrode located in a first device level and a second control gate electrode located in a second device level located over the major surface of the substrate and below the first device level. The device also includes an etch stop layer located between the substrate and the plurality of control gate electrodes.

    摘要翻译： 一种包括衬底和半导体沟道的三维存储器件。 半导体通道的至少一个端部基本上垂直于衬底的主表面延伸。 该器件还包括位于半导体通道附近的至少一个电荷存储区域以及具有基本上平行于衬底的主表面延伸的条带形状的多个控制栅极电极。 多个控制栅电极至少包括位于第一器件级的第一控制栅电极和位于位于衬底的主表面上方且低于第一器件电平的第二器件电平的第二控制栅电极。 该器件还包括位于衬底和多个控制栅电极之间的蚀刻停止层。

    MULTILEVEL MEMORY STACK STRUCTURE EMPLOYING SUPPORT PILLAR STRUCTURES
    50.
    发明申请
    MULTILEVEL MEMORY STACK STRUCTURE EMPLOYING SUPPORT PILLAR STRUCTURES 有权
    多层记忆体结构采用支撑支柱结构

    公开(公告)号：US20160322381A1

    公开(公告)日：2016-11-03

    申请号：US14862916

    申请日：2015-09-23

    申请人： SANDISK TECHNOLOGIES INC.

    发明人： Jin Liu ,  Tong Zhang ,  Jayavel Pachamuthu ,  Yao-Sheng Lee ,  Johann Alsmeier

    IPC分类号： H01L27/115 ,  H01L21/768 ,  H01L29/417 ,  H01L21/28 ,  H01L29/788 ,  H01L23/528

    CPC分类号： H01L27/11582 ,  H01L21/28273 ,  H01L21/28282 ,  H01L21/76802 ,  H01L21/76877 ,  H01L23/528 ,  H01L27/11526 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11575 ,  H01L29/41741 ,  H01L29/7883

    摘要： A first stack of alternating layers including first electrically insulating layers and first sacrificial material layers is formed with first stepped surfaces. First memory openings can be formed in a device region outside of the first stepped surfaces, and first support openings can be formed through the first stepped surfaces. The first memory openings and the first support openings can be filled with a sacrificial fill material. A second stack of alternating layers including second electrically insulating layers and second sacrificial material layers can be formed over the first stack. Inter-stack memory openings including the first memory openings can be formed in the device region, and inter-stack support openings including the first support openings can be formed in a steppes surface region. Memory stack structures and support pillar structure are simultaneously formed in the inter-stack memory openings and the inter-stack support openings, respectively.

    摘要翻译： 包括第一电绝缘层和第一牺牲材料层的交替层的第一堆叠形成有第一台阶表面。 第一存储器开口可以形成在第一台阶表面外部的器件区域中，并且可以通过第一台阶表面形成第一支撑开口。 第一存储器开口和第一支撑开口可以填充牺牲填充材料。 可以在第一堆叠上形成包括第二电绝缘层和第二牺牲材料层的交替层的第二堆叠。 包括第一存储器开口的堆叠间存储器开口可以形成在器件区域中，并且包括第一支撑开口的堆叠间支撑开口可以形成在草原表面区域中。 存储堆栈结构和支撑柱结构分别同时形成在堆叠间存储器开口和堆叠间支撑开口中。