公开(公告)号：US10312244B2

公开(公告)日：2019-06-04

申请号：US15708913

申请日：2017-09-19

Applicant: QUALCOMM Incorporated

Inventor： Xia Li ,  Seung Hyuk Kang ,  Bin Yang ,  Gengming Tao

IPC: H01L27/11 ,  H01L29/08 ,  H01L29/10 ,  H01L29/06 ,  H01L29/423 ,  H01L29/417 ,  H01L29/165 ,  H01L29/16 ,  H01L21/762 ,  H01L21/027 ,  H01L21/306 ,  H01L21/3105 ,  G11C11/419 ,  H01L27/07

Abstract: Bi-stable static random access memory (SRAM) bit cells that facilitate direct writing for storage are disclosed. In one aspect, a bi-stable SRAM bit cell includes source and drain regions, and a gate region formed over a well region between the source and drain regions, which results in two (2) bipolar junction transistors (BJTs) formed within a bi-stable SRAM bit cell. A base tap region and a collector tap region are employed to provide voltages for read and write operations. The base tap region is formed beside a shallow trench isolation (STI) region having a bottom surface higher in a Y-axis direction in the well region than a bottom surface of the well region. The collector tap region is formed on one side of an STI region having a bottom surface lower in the Y-axis direction in the substrate than the bottom surface of the well region.

公开(公告)号：US10283650B2

公开(公告)日：2019-05-07

申请号：US15659718

申请日：2017-07-26

Applicant: QUALCOMM Incorporated

Inventor： Xia Li ,  Bin Yang ,  Gengming Tao

IPC: H01L27/108 ,  H01L29/94 ,  H01L29/66 ,  H01L29/93 ,  H01L29/06

Abstract: Certain aspects of the present disclosure generally relate to a semiconductor variable capacitor offering at least two types of capacitance tuning, as well as techniques for fabricating the same. For example, a CMOS-compatible silicon on insulator (SOI) process with a buried oxide (BOX) layer may provide a transcap with a front gate (above the BOX layer) and a back gate (beneath the BOX layer). The front gate may offer lower voltage, coarse capacitance tuning, whereas the back gate may offer higher voltage, fine capacitance tuning. By offering both types of capacitance tuning, such transcaps may provide greater capacitance resolution. Several variations of transcaps with front gate and back gate tuning are illustrated and described herein.

公开(公告)号：US10164054B2

公开(公告)日：2018-12-25

申请号：US15683530

申请日：2017-08-22

Applicant: QUALCOMM Incorporated

Inventor： Bin Yang ,  Gengming Tao ,  Xia Li ,  Periannan Chidambaram

IPC: H01L29/66 ,  H01L29/40 ,  H01L29/423 ,  H01L29/778 ,  H01L21/768 ,  H01L29/812

Abstract: A compound semiconductor field effect transistor (FET) may include a channel layer. The semiconductor FET may also include an oxide layer, partially surrounded by a passivation layer, on the channel layer. The semiconductor FET may also include a first dielectric layer on the oxide layer. The semiconductor FET may also include a second dielectric layer on the first dielectric layer. The semiconductor FET may further include a gate, comprising a base gate through the oxide layer and the first dielectric layer, and a head gate in the second dielectric layer and electrically coupled to the base gate.

公开(公告)号：US10109724B2

公开(公告)日：2018-10-23

申请号：US15614471

申请日：2017-06-05

Applicant: QUALCOMM Incorporated

Inventor： Gengming Tao ,  Bin Yang ,  Xia Li ,  Miguel Miranda Corbalan

IPC: H01L29/73 ,  H01L29/737 ,  H01L29/08 ,  H01L29/10 ,  H01L29/66 ,  H01L29/06

Abstract: A heterojunction bipolar transistor unit cell may include a compound semiconductor substrate. The heterojunction bipolar transistor unity may also include a base mesa on the compound semiconductor substrate. The base mesa may include a collector region on the compound semiconductor substrate and a base region on the collector region. The heterojunction bipolar transistor unity may further include a single emitter mesa on the base mesa.

公开(公告)号：US10043826B1

公开(公告)日：2018-08-07

申请号：US15660288

申请日：2017-07-26

Applicant: QUALCOMM Incorporated

Inventor： Xia Li ,  Bin Yang ,  Gengming Tao

IPC: H01L29/423 ,  H01L27/12 ,  H01L29/08 ,  H01L29/36 ,  H01L29/10 ,  H01L29/06 ,  H01L29/78 ,  H01L29/45 ,  H01L21/762 ,  H01L29/66 ,  H01L21/265 ,  H01L21/84 ,  H01L21/683 ,  H01L21/02 ,  H01L21/8234

Abstract: Certain aspects of the present disclosure generally relate to a semiconductor device. The semiconductor device generally includes a substrate, a first non-insulative region disposed above the substrate, and a second non-insulative region disposed above the first non-insulative region, wherein the first and second non-insulative regions have the same doping type and different doping concentrations. In certain aspects, the semiconductor device also includes a first dielectric layer, a channel region, the first dielectric layer being disposed adjacent to a first side of the channel region, a second dielectric layer disposed adjacent to a second side of the channel region, and a third non-insulative region disposed above the second dielectric layer. In certain aspects, the semiconductor device also includes a fourth non-insulative region disposed adjacent to a third side of the channel region, and a fifth non-insulative region disposed adjacent to a fourth side of the channel region.