公开(公告)号：US11791276B2

公开(公告)日：2023-10-17

申请号：US17225949

申请日：2021-04-08

Applicant: QUALCOMM Incorporated

Inventor： Aniket Patil ,  Hong Bok We ,  Joan Rey Villarba Buot

IPC: H01L23/538 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31 ,  H01L23/00

CPC classification number: H01L23/5389 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/565 ,  H01L23/3128 ,  H01L23/5383 ,  H01L23/5385 ,  H01L23/5386 ,  H01L24/16 ,  H01L2224/16227 ,  H01L2924/19103 ,  H01L2924/19105

Abstract: A device comprising a first substrate comprising a first plurality of pillar interconnects; a second substrate comprising a second plurality of pillar interconnects, wherein the second plurality of pillar interconnects is coupled to the first plurality of pillar interconnects through a plurality of solder interconnects; a passive component located between the first substrate and the second substrate; and an integrated device coupled to the first substrate.

公开(公告)号：US11784151B2

公开(公告)日：2023-10-10

申请号：US16936263

申请日：2020-07-22

Applicant: QUALCOMM Incorporated

Inventor： Aniket Patil ,  Hong Bok We ,  Marcus Hsu

IPC: H01L23/00

CPC classification number: H01L24/20 ,  H01L24/19 ,  H01L2224/2101 ,  H01L2924/01029 ,  H01L2924/30101

Abstract: Examples herein include die to metallization structure connections that eliminate the solder joint to reduce the resistance and noise on the connection. In one example, a first die is attached to a metallization layer by a plurality of copper interconnections and a second is attached to the metallization layer opposite the first die through another plurality of copper interconnections. In this example, the copper interconnects may connect the respective die to a metallization structure in the metallization layer.

公开(公告)号：US11749611B2

公开(公告)日：2023-09-05

申请号：US17164723

申请日：2021-02-01

Applicant: QUALCOMM Incorporated

Inventor： Aniket Patil ,  Hong Bok We

IPC: H01L23/00 ,  H01L23/538 ,  H01L25/065 ,  H01L25/18 ,  H01L25/00

CPC classification number: H01L23/5386 ,  H01L24/16 ,  H01L25/0655 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/16227

Abstract: A package comprising a substrate, a first integrated device and a second integrated device. The substrate includes at least one dielectric layer, a plurality of interconnects, a solder resist layer, and a plurality of periphery interconnects located over the solder resist layer. The first integrated device is coupled to the substrate. The second integrated device is coupled to the substrate. The second integrated device is configured to be electrically coupled to the first integrated device through the plurality of periphery interconnects.

公开(公告)号：US11682607B2

公开(公告)日：2023-06-20

申请号：US17164729

申请日：2021-02-01

Applicant: QUALCOMM Incorporated

Inventor： Hong Bok We ,  Marcus Hsu ,  Aniket Patil

IPC: H01L21/00 ,  H01L23/48 ,  H01L21/768 ,  H01L23/00

CPC classification number: H01L23/481 ,  H01L21/76898 ,  H01L24/14 ,  H01L24/81 ,  H01L2224/1403 ,  H01L2224/1412 ,  H01L2224/14051

Abstract: A package that includes a substrate and an integrated device. The substrate includes at least one dielectric layer, a plurality of interconnects comprising a first material, and a plurality of surface interconnects coupled to the plurality of interconnects. The plurality of surface interconnects comprises a second material. A surface of the plurality of surface interconnects is planar with a surface of the substrate. The integrated device is coupled to the plurality of surface interconnects of the substrate through a plurality of pillar interconnects and a plurality of solder interconnects.

公开(公告)号：US20230083146A1

公开(公告)日：2023-03-16

申请号：US17474524

申请日：2021-09-14

Applicant: QUALCOMM Incorporated

Inventor： Hong Bok We ,  Joan Rey Villarba Buot ,  Aniket Patil

IPC: H01Q1/22 ,  H01Q1/52 ,  H01Q1/42 ,  H01Q9/04 ,  H01Q21/06 ,  H01Q1/38

Abstract: Multi-sided antenna modules employing antennas on multiple sides of a package substrate for enhanced antenna coverage, and related antenna module fabrication methods. The multi-sided antenna module includes an integrated circuit (IC) die(s) disposed on a first side of the package substrate. The multi-sided antenna module further includes first and second substrate antenna layers disposed on respective first and second sides of the package substrate. The first substrate antenna layer includes a first antenna(s) disposed on the first side of the package substrate adjacent to the IC die(s). The second substrate antenna layer includes a second antenna(s) disposed on the second side of the package substrate opposite of the first side of the package substrate. In this manner, the multi-sided antenna module, including antennas on multiple sides of the package substrate, provides antenna coverage that extends from both sides of the package substrate to provide multiple directions of coverage.

公开(公告)号：US20230035627A1

公开(公告)日：2023-02-02

申请号：US17443740

申请日：2021-07-27

Applicant: QUALCOMM Incorporated

Inventor： Aniket Patil ,  Brigham Navaja ,  Hong Bok We

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/31 ,  H01L25/00

Abstract: Split die IC packages employing a D2D interconnect structure in a die-substrate standoff cavity (i.e., cavity) to provide D2D connections, and related fabrication methods. To facilitate D2D communications between multiple dies in the split die IC package, the package substrate also includes a D2D interconnect structure (e.g., interconnect bridge) that contains D2D interconnects (e.g., metal interconnects) coupled to the multiple dies to provide D2D signal routing between the multiple dies. The D2D interconnect structure is disposed in a cavity that is formed in a die standoff area between the dies and the package substrate as a result of the die interconnects being disposed between the dies and the package substrate standing off the dies from the package substrate. The D2D interconnect structure can be provided in the cavity in the IC package outside of the package substrate to reserve more area in the package substrate for other interconnections.

公开(公告)号：US11545435B2

公开(公告)日：2023-01-03

申请号：US16946104

申请日：2020-06-05

Applicant: QUALCOMM Incorporated

Inventor： Kuiwon Kang ,  Zhijie Wang ,  Hong Bok We

IPC: H01L23/538 ,  H01L25/065 ,  H01L23/498

Abstract: Some features pertain to a substrate that includes a first portion of the substrate including a first plurality of metal layers, a second portion of the substrate including a second plurality of metal layers, and a plurality of insulating layers configured to separate the first plurality of metal layers and the second plurality of metal layers. A first plurality of posts and a plurality of interconnects are coupled together such that the first plurality of posts and the plurality of interconnects couple the first portion of the substrate to the second portion of the substrate.

公开(公告)号：US11502049B2

公开(公告)日：2022-11-15

申请号：US16868349

申请日：2020-05-06

Applicant: QUALCOMM Incorporated

Inventor： Aniket Patil ,  David Fraser Rae ,  Hong Bok We

IPC: H01L23/00 ,  H01L23/31 ,  H01L21/56

Abstract: A package that includes a first redistribution portion, a second redistribution portion, a third redistribution portion, a first encapsulation layer coupled to the first redistribution portion and the third redistribution portion, a first discrete device encapsulated by the first encapsulation layer, wherein the first discrete device is located between the first redistribution portion and the third redistribution portion, a second encapsulation layer coupled to the first redistribution portion and the second redistribution portion, and a second discrete device encapsulated by the second encapsulation layer, wherein the second discrete device is located between the first redistribution portion and the second redistribution portion.

公开(公告)号：US11444019B2

公开(公告)日：2022-09-13

申请号：US16840752

申请日：2020-04-06

Applicant: QUALCOMM Incorporated

Inventor： Aniket Patil ,  Hong Bok We ,  Kuiwon Kang

IPC: H01L23/522 ,  H01L21/56 ,  H01L23/31 ,  H01L23/498 ,  H01L23/538 ,  H01L23/00

Abstract: A package comprising a substrate and an integrated device coupled to the substrate. The substrate includes (i) at least one inner dielectric layer, (ii) a plurality of interconnects located in the at least one inner dielectric layer, where the plurality of interconnects includes a pad located on a bottom metal layer of the substrate, (iii) an outer dielectric layer located over the at least one dielectric layer, (iv) at least one routing interconnect coupled to the plurality of interconnects, where the at least one routing interconnect is located over the outer dielectric layer, where the at least one routing interconnect is located below the bottom metal layer of the substrate, and (v) a cover dielectric layer located over the outer dielectric layer and the at least one routing interconnect. The package includes a solder interconnect coupled to the pad located on the bottom metal layer of the substrate.

公开(公告)号：US11302656B2

公开(公告)日：2022-04-12

申请号：US16938316

申请日：2020-07-24

Applicant: QUALCOMM Incorporated

Inventor： Hong Bok We ,  Aniket Patil ,  Joan Rey Villarba Buot ,  Zhijie Wang

IPC: H01L23/64 ,  H01L21/48 ,  H01L23/498 ,  H01L23/00 ,  H01L25/065

Abstract: An integrated circuit (IC) package is described. The IC package includes a package substrate, composed of a substrate core, a first power rail on a first surface of the substrate core, and a second power rail on a second surface of the substrate core. The IC package includes a logic die supported by the second power rail on the second surface of the substrate core. The IC package includes passive devices within the substrate core. Each of the passive devices has a first terminal and a second terminal opposite the first terminal. The first terminal of each of the passive devices is directly coupled to the first power rail, and the second terminal of each of the plurality of the passive devices is directly coupled to the second power rail. The IC package includes package bumps on the second power rail on the second surface of the substrate core.