公开(公告)号：US11509308B1

公开(公告)日：2022-11-22

申请号：US17407909

申请日：2021-08-20

Applicant: Kepler Computing Inc.

Inventor： Amrita Mathuriya ,  Ikenna Odinaka ,  Rajeev Kumar Dokania ,  Rafael Rios ,  Sasikanth Manipatruni

IPC: H03K3/12 ,  H03K19/185 ,  H03K19/17736 ,  H01L49/02 ,  G11C7/10

Abstract: A low power sequential circuit (e.g., latch) uses a non-linear polar capacitor to retain charge with fewer transistors than traditional CMOS sequential circuits. In one example, a sequential circuit includes pass-gates and inverters, but without a feedback mechanism or memory element. In another example, a sequential uses load capacitors (e.g., capacitors coupled to a storage node and a reference supply). The load capacitors are implemented using ferroelectric material, paraelectric material, or linear dielectric. In one example, a sequential uses minority, majority, or threshold gates with ferroelectric or paraelectric capacitors. In one example, a sequential circuit uses minority, majority, or threshold gates configured as NAND gates.

公开(公告)号：US11501813B1

公开(公告)日：2022-11-15

申请号：US17390791

申请日：2021-07-30

Applicant: Kepler Computing Inc.

Inventor： Rajeev Kumar Dokania ,  Noriyuki Sato ,  Tanay Gosavi ,  Pratyush Pandey ,  Debo Olaosebikan ,  Amrita Mathuriya ,  Sasikanth Manipatruni

IPC: G11C11/22 ,  G11C11/417

Abstract: A high-density low voltage ferroelectric (or paraelectric) memory bit-cell that includes a planar ferroelectric or paraelectric capacitor. The memory bit-cell comprises 1T1C configuration, where a plate-line is parallel to a word-line, or the plate-line is parallel to a bit-line. The memory bit-cell can be 1TnC, where ‘n’ is a number. In a 1TnC bit-cell, the capacitors are vertically stacked allowing for multiple values to be stored in a single bit-cell. The memory bit-cell can be multi-element FE gain bit-cell. In a multi-element FE gain bit-cell, data sensing is done with signal amplified by a gain transistor in the bit-cell. As such, higher storage density is realized using multi-element FE gain bit-cells. In some examples, the 1T1C, 1TnC, and multi-element FE gain bit-cells are multi-level bit-cells. To realize multi-level bit-cells, the capacitor is placed in a partially switched polarization state by applying different voltage levels or different time pulse widths at the same voltage level.

公开(公告)号：US11482529B2

公开(公告)日：2022-10-25

申请号：US16288004

申请日：2019-02-27

Applicant: Kepler Computing Inc.

Inventor： Sasikanth Manipatruni ,  Rajeev Kumar Dokania ,  Ramamoorthy Ramesh

IPC: H01L27/11507 ,  H01L49/02 ,  G11C11/22 ,  H01L27/11514 ,  H01L21/02 ,  G11C11/402 ,  H01L27/108 ,  H01L29/78

Abstract: Described is a low power, high-density a 1T-1C (one transistor and one capacitor) memory bit-cell, wherein the capacitor comprises a pillar structure having ferroelectric material (perovskite, improper ferroelectric, or hexagonal ferroelectric) and conductive oxides as electrodes. In various embodiments, one layer of the conductive oxide electrode wraps around the pillar capacitor, and forms the outer electrode of the pillar capacitor. The core of the pillar capacitor can take various forms.

公开(公告)号：US11451232B2

公开(公告)日：2022-09-20

申请号：US17390830

申请日：2021-07-30

Applicant: Kepler Computing Inc.

Inventor： Sasikanth Manipatruni ,  Yuan-Sheng Fang ,  Robert Menezes ,  Rajeev Kumar Dokania ,  Ramamoorthy Ramesh ,  Amrita Mathuriya

IPC: H03K19/23 ,  H03K19/00 ,  H03K19/21

Abstract: A low power sequential circuit (e.g., latch) uses a non-linear polar capacitor to retain charge with fewer transistors than traditional CMOS sequential circuits. The sequential circuit includes a 3-input majority gate having first, second, and third inputs, and a first output. The sequential circuit includes a driver coupled to the first output, wherein the driver is to generate a second output. The sequential circuit further includes an exclusive-OR (XOR) gate to receive a clock and the second output, wherein the XOR gate is to generate a third output which couples to the second input, where the first input is to receive a data, and wherein the third input is to receive the second output.

公开(公告)号：US20220278116A1

公开(公告)日：2022-09-01

申请号：US17663187

申请日：2022-05-12

Applicant: Kepler Computing Inc.

Inventor： Sasikanth Manipatruni ,  Rajeev Kumar Dokania ,  Ramamoorthy Ramesh ,  Gaurav Thareja ,  Amrita Mathuriya

IPC: H01L27/11507 ,  H01L49/02 ,  G11C11/22

Abstract: Approaches for integrating FE memory arrays into a processor, and the resulting structures are described. Simultaneous integrations of regions with ferroelectric (FE) cells and regions with standard interconnects are also described. FE cells include FE capacitors that include a FE stack of layers, which is encapsulated with a protection material. The protection material protects the FE stack of layers as structures for regular logic are fabricated in the same die.

公开(公告)号：US11423967B1

公开(公告)日：2022-08-23

申请号：US17359311

申请日：2021-06-25

Applicant: Kepler Computing Inc.

Inventor： Rajeev Kumar Dokania ,  Noriyuki Sato ,  Tanay Gosavi ,  Pratyush Pandey ,  Debo Olaosebikan ,  Amrita Mathuriya ,  Sasikanth Manipatruni

IPC: G11C11/22 ,  G11C11/417

Abstract: A high-density low voltage ferroelectric (or paraelectric) memory bit-cell that includes a planar ferroelectric or paraelectric capacitor. The memory bit-cell comprises 1T1C configuration, where a plate-line is parallel to a word-line, or the plate-line is parallel to a bit-line. The memory bit-cell can be 1TnC, where ‘n’ is a number. In a 1TnC bit-cell, the capacitors are vertically stacked allowing for multiple values to be stored in a single bit-cell. The memory bit-cell can be multi-element FE gain bit-cell. In a multi-element FE gain bit-cell, data sensing is done with signal amplified by a gain transistor in the bit-cell. As such, higher storage density is realized using multi-element FE gain bit-cells. In some examples, the 1T1C, 1TnC, and multi-element FE gain bit-cells are multi-level bit-cells. To realize multi-level bit-cells, the capacitor is placed in a partially switched polarization state by applying different voltage levels or different time pulse widths at the same voltage level.

公开(公告)号：US11295796B1

公开(公告)日：2022-04-05

申请号：US17344817

申请日：2021-06-10

Applicant: Kepler Computing Inc.

Inventor： Christopher B. Wilkerson ,  Sasikanth Manipatruni ,  Rajeev Kumar Dokania ,  Amrita Mathuriya

IPC: G11C13/00 ,  G11C11/22 ,  G11C11/16 ,  G11C16/10

Abstract: Endurance mechanisms are introduced for memories such as non-volatile memories for broad usage including caches, last-level cache(s), embedded memory, embedded cache, scratchpads, main memory, and storage devices. Here, non-volatile memories (NVMs) include magnetic random-access memory (MRAM), resistive RAM (ReRAM), ferroelectric RAM (FeRAM), phase-change memory (PCM), etc. In some cases, features of endurance mechanisms (e.g., randomizing mechanisms) are applicable to volatile memories such as static random-access memory (SRAM), and dynamic random-access memory (DRAM). The endurance mechanisms include a wear leveling scheme that uses index rotation, outlier compensation to handle weak bits, and random swap injection to mitigate wear out attacks.

公开(公告)号：US11289497B2

公开(公告)日：2022-03-29

申请号：US16729273

申请日：2019-12-27

Applicant: Kepler Computing, Inc.

Inventor： Gaurav Thareja ,  Sasikanth Manipatruni ,  Rajeev Kumar Dokania ,  Ramamoorthy Ramesh ,  Amrita Mathuriya

IPC: H01L27/11507 ,  H01L49/02 ,  G11C11/22

Abstract: Approaches for integrating FE memory arrays into a processor, and the resulting structures are described. Simultaneous integrations of regions with ferroelectric (FE) cells and regions with standard interconnects are also described. FE cells include FE capacitors that include a FE stack of layers, which is encapsulated with a protection material. The protection material protects the FE stack of layers as structures for regular logic are fabricated in the same die.

公开(公告)号：US11165430B1

公开(公告)日：2021-11-02

申请号：US17129842

申请日：2020-12-21

Applicant: Kepler Computing, Inc.

Inventor： Sasikanth Manipatruni ,  Yuan-Sheng Fang ,  Robert Menezes ,  Rajeev Kumar Dokania ,  Gaurav Thareja ,  Ramamoorthy Ramesh ,  Amrita Mathuriya

IPC: H03K19/23 ,  H03K19/00 ,  H03K19/21

Abstract: A low power sequential circuit (e.g., latch) uses a non-linear polar capacitor to retain charge with fewer transistors than traditional CMOS sequential circuits. The sequential circuit includes a 3-input majority gate having first, second, and third inputs, and a first output. The sequential circuit includes a driver coupled to the first output, wherein the driver is to generate a second output. The sequential circuit further includes an exclusive-OR (XOR) gate to receive a clock and the second output, wherein the XOR gate is to generate a third output which couples to the second input, where the first input is to receive a data, and wherein the third input is to receive the second output.

公开(公告)号：US10951213B1

公开(公告)日：2021-03-16

申请号：US16797296

申请日：2020-02-21

Applicant: Kepler Computing, Inc.

Inventor： Sasikanth Manipatruni ,  Robert Menezes ,  Yuan-Sheng Fang ,  Rajeev Kumar Dokania ,  Gaurav Thareja ,  Ramamoorthy Ramesh ,  Amrita Mathuriya

IPC: H03K19/00 ,  H01L27/118 ,  H03K19/23 ,  H01L49/02 ,  H01L29/51 ,  H03K19/20 ,  H01L27/11502

Abstract: A new class of logic gates are presented that use non-linear polar material. The logic gates include multi-input majority gates and threshold gates. Input signals in the form of analog, digital, or combination of them are driven to first terminals of non-ferroelectric capacitors. The second terminals of the non-ferroelectric capacitors are coupled to form a majority node. Majority function of the input signals occurs on this node. The majority node is then coupled to a first terminal of a capacitor comprising non-linear polar material. The second terminal of the capacitor provides the output of the logic gate, which can be driven by any suitable logic gate such as a buffer, inverter, NAND gate, NOR gate, etc. Any suitable logic or analog circuit can drive the output and inputs of the majority logic gate. As such, the majority gate of various embodiments can be combined with existing transistor technologies.