公开(公告)号：US20230317727A1

公开(公告)日：2023-10-05

申请号：US17706675

申请日：2022-03-29

Applicant: International Business Machines Corporation

Inventor： Chen Zhang ,  Julien Frougier ,  Ruilong Xie ,  Heng Wu

IPC: H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L23/532 ,  H01L23/535 ,  H01L21/8238

CPC classification number: H01L27/0922 ,  H01L27/0924 ,  H01L29/0665 ,  H01L29/42392 ,  H01L29/78696 ,  H01L23/53257 ,  H01L23/535 ,  H01L21/823821 ,  H01L21/823871

Abstract: A set of stacked transistors, system, and method to connect the gates of stacked field-effect transistors through sidewall straps. The set of stacked transistors may include a first transistor including a first gate. The set of stacked transistors may also include a second transistor including a second gate, where the second transistor is above the first transistor. The set of stacked transistors may also include a dielectric preventing direct contact between the first gate and the second gate. The set of stacked transistors may also include a first sidewall strap proximately connected to the first gate and the second gate, where the first sidewall strap connects the first transistor and the second transistor.

公开(公告)号：US20230261049A1

公开(公告)日：2023-08-17

申请号：US17673775

申请日：2022-02-16

Applicant: International Business Machines Corporation

Inventor： Ruilong Xie ,  Hemanth Jagannathan ,  Oleg Gluschenkov ,  Julien Frougier

IPC: H01L29/06 ,  H01L29/78 ,  H01L29/66 ,  H01L29/786 ,  H01L29/423

CPC classification number: H01L29/0665 ,  H01L29/7827 ,  H01L29/42392 ,  H01L29/66666 ,  H01L29/78696

Abstract: A semiconductor structure includes a semiconductor channel structure that has a body and a tip and a dielectric spacer adjacent to the tip. The tip is no less than 70% the thickness of the body.

公开(公告)号：US20230215768A1

公开(公告)日：2023-07-06

申请号：US17566402

申请日：2021-12-30

Applicant: International Business Machines Corporation

Inventor： Ruilong Xie ,  Julien Frougier ,  Heng Wu ,  Nicolas Loubet

IPC: H01L21/8238 ,  H01L29/423 ,  H01L29/06 ,  H01L29/78

CPC classification number: H01L21/823807 ,  H01L21/823821 ,  H01L29/0665 ,  H01L29/785 ,  H01L29/42392

Abstract: An exemplary semiconductor apparatus includes a substrate that includes a first semiconductor. The substrate includes a main body and first and second island portions protruding upward from the main body. The apparatus also includes a bottom dielectric isolation layer that covers the substrate; a PFET with a plurality of gate-all-around (GAA) vertical channel fins above the first island portion and the bottom dielectric isolation layer; and an NFET with a plurality of gate-all-around (GAA) horizontal nanosheet layers above the second island portion and the bottom dielectric isolation layer.

公开(公告)号：US20230207622A1

公开(公告)日：2023-06-29

申请号：US17561636

申请日：2021-12-23

Applicant: International Business Machines Corporation

Inventor： HUIMEI ZHOU ,  Ruilong Xie ,  Julien Frougier ,  MIAOMIAO WANG

IPC: H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L29/66 ,  H01L21/8234 ,  H01L23/528

CPC classification number: H01L29/0665 ,  H01L29/42392 ,  H01L29/78618 ,  H01L29/78696 ,  H01L29/0649 ,  H01L29/66742 ,  H01L21/823412 ,  H01L21/823418 ,  H01L23/5286

Abstract: Vertically stacked, buried power rails are electrically connected to wrap-around contacts or other electrically conductive liners on transistor source/drain regions. The buried power rails are electrically isolated from each other by an electrical insulator. Wrap-around contacts can be electrically connected to different ones of the vertically stacked, buried power rails or to the same buried power rail.

公开(公告)号：US20230178422A1

公开(公告)日：2023-06-08

申请号：US17643202

申请日：2021-12-08

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Ruilong Xie ,  Julien Frougier ,  Nicolas Loubet ,  Kangguo Cheng ,  CHANRO PARK

IPC: H01L21/768 ,  H01L23/522

CPC classification number: H01L21/76816 ,  H01L23/5226 ,  H01L21/76804 ,  H01L21/76843

Abstract: An interconnect structure and a method of forming the interconnect structure are provided. The interconnect structure includes a source drain contact above and contacting a source drain region of a semiconductor device. The interconnect structure also includes a via above and contacting the source drain contact. The via includes a lower portion with an uppermost surface that contacts a lowermost surface of an interlayer dielectric.

公开(公告)号：US20230170396A1

公开(公告)日：2023-06-01

申请号：US17538205

申请日：2021-11-30

Applicant: International Business Machines Corporation

Inventor： Julien Frougier ,  Ruilong Xie ,  Kangguo Cheng ,  Chanro Park ,  Andrew Gaul

IPC: H01L29/423 ,  H01L29/786 ,  H01L29/06 ,  H01L29/66

CPC classification number: H01L29/42392 ,  H01L29/78696 ,  H01L29/0673 ,  H01L29/66969

Abstract: Embodiments herein describe FETs with channels connected on the sides to a metal liner. To avoid the difficulties of connecting the sides of the channels to metal liners for the drain and source regions, the embodiments herein form a male/female contact between the channels and the metal liners. In one embodiment, instead of exposing only the end or side surfaces of the channels, an end knob of the channel is exposed. This knob can include the side surface as well as a portion of the top, bottom, front, and back sides of the channel. As such, when the metal liner is deposited on the knob, this metal forms an electrical connection on all sides of the knob. This male/female connection provides a more reliable and lower resistance connection between the channel and the metal liner than using only the end or side surfaces of the channel.

公开(公告)号：US20230142410A1

公开(公告)日：2023-05-11

申请号：US17453882

申请日：2021-11-08

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Julien Frougier ,  Ruilong Xie ,  Heng Wu ,  Chen Zhang ,  Alexander Reznicek

IPC: H01L29/06 ,  H01L29/66 ,  H01L29/423

CPC classification number: H01L29/0673 ,  H01L29/66553 ,  H01L29/42392

Abstract: A semiconductor device comprising a first nanosheet located on top of a substrate, wherein the first nanosheet is tapered the Y-direction to have a width W1 and the first nanosheet is tapered in the X-direction to have a length L1. A second nanosheet located on top of the first nanosheet, wherein the second nanosheets is tapered in the Y-direction to have a width W2 and the first nanosheet is tapered in the X-direction to have a length L2. Wherein the widths W1 and W2 are different from each other and the lengths L1 and L2 are different from each other and wherein the substrate includes a tapered surface in the Y-direction.

公开(公告)号：US20230133545A1

公开(公告)日：2023-05-04

申请号：US17518515

申请日：2021-11-03

Applicant: International Business Machines Corporation

Inventor： Julien Frougier ,  Nicolas Loubet ,  Andrew M. Greene ,  Ruilong Xie ,  Maruf Amin Bhuiyan ,  Veeraraghavan S. Basker

IPC: H01L29/423 ,  H01L29/06 ,  H01L29/66

Abstract: A semiconductor device includes a semiconductor substrate, a first pair of FET (field effect transistor) gate structures separated by a first gate canyon having a first gate canyon spacing, disposed upon the semiconductor substrate, a second pair of FET gate structures separated by a second gate canyon having a second gate canyon spacing, disposed upon the substrate, a first S/D (source/drain region disposed in the first gate canyon, a second S/D region disposed in the second gate canyon, a first BDI (bottom dielectric isolation) element disposed below the first S/D region and having a first BDI thickness, and a second BDI element disposed below the second S/D region and having a second BDI thickness. The first BDI thickness exceeds the second BDI thickness.

公开(公告)号：US20230123883A1

公开(公告)日：2023-04-20

申请号：US17485333

申请日：2021-09-25

Applicant: International Business Machines Corporation

Inventor： Ruilong Xie ,  Julien Frougier ,  Kangguo Cheng ,  Chanro Park ,  Cheng Chi ,  Jinning Liu

IPC: H01L29/423 ,  H01L29/06 ,  H01L29/786 ,  H01L27/088 ,  H01L21/8234

Abstract: A semiconductor structure comprises a substrate defining a first axis and a second axis orthogonal to the first axis, a first nanosheet region disposed on the substrate and defining a first channel width along the second axis, a first gate disposed around the first nanosheet region, a second nanosheet region disposed on the substrate and defining a second channel width along the second axis less than the first channel width of the first nanosheet region and a second gate disposed around the second nanosheet region.

公开(公告)号：US20230095447A1

公开(公告)日：2023-03-30

申请号：US17489751

申请日：2021-09-29

Applicant: International Business Machines Corporation

Inventor： Ruilong Xie ,  Julien Frougier ,  Kangguo Cheng ,  CHANRO PARK

IPC: H01L29/417 ,  H01L29/423 ,  H01L29/06 ,  H01L29/66 ,  H01L29/786

Abstract: A semiconductor structure includes a substrate; bottom dielectric isolation (BDI) on the substrate; a first source/drain region on the BDI; and a nanosheet stack on the BDI. The nanosheet stack includes gate stack layers; semiconductor nanosheets interleaved with the gate stack layers and contacting the first source/drain region; and first inner spacers adjacent to the first source/drain region and separating the first source/drain region from the gate stack layers. The structure also includes a second source/drain region contacting the semiconductor nanosheet and extending from the top of the nanosheet stack down through the BDI to the substrate. Accordingly, the nanosheet stack also includes second inner spacers in the nanosheet stack adjacent to the second source/drain region and separating the second source/drain region from the gate stack layers.