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    Reconfigurable ring oscillator (RO) physical unclonable function (PUF)
    42.
    发明授权
    Reconfigurable ring oscillator (RO) physical unclonable function (PUF) 有权

    公开(公告)号：US12255651B1

    公开(公告)日：2025-03-18

    申请号：US18494379

    申请日：2023-10-25

    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

    Inventor： Kangguo Cheng ,  Julien Frougier ,  Carl Radens ,  Ruilong Xie

    IPC: H03K3/03 ,  G06F7/58 ,  G06F21/73 ,  H03K3/84 ,  H04L9/32

    Abstract: Provided is a reconfigurable Ring Oscillator (RO) Physical Unclonable Function (PUF), which comprises a NAND gate with a first input line and a second input line and a series of inverters with at least one memory cell placed between two inverters of the series of inverters, where an output of a last inverter provides input to the second input line, and where the memory cell comprises a Field Effect Transistor (FET). In addition, the reconfigurable RO PUF comprises a frequency counter, where the output of the last inverter provides input to the frequency counter. In normal operation mode, the first input line is on to enable ring oscillation and the FET is off. In reconfiguration mode, the first input line is off and the FET is on to enable reconfiguration.

    BACKSIDE PROGRAMMABLE MEMORY
    43.
    发明公开
    BACKSIDE PROGRAMMABLE MEMORY 审中-公开

    公开(公告)号：US20240164089A1

    公开(公告)日：2024-05-16

    申请号：US18054161

    申请日：2022-11-10

    Applicant: International Business Machines Corporation

    Inventor： Albert M. Chu ,  Junli Wang ,  Albert M. Young ,  Brent A. Anderson ,  Ruilong Xie ,  Carl Radens

    IPC: H01L27/112

    CPC classification number: H01L27/11206

    Abstract: Embodiments of the present invention are directed to processing methods and resulting structures having backside programmable memory cells. In a non-limiting embodiment, a front end of line structure having a plurality of programmable cells is formed such that each programmable cell includes a backside via in direct contact with a device region of the respective cell. A first portion of the backside vias defines one or more placeholder backside vias and a second portion defines one or more programmed backside vias. A back end of line structure (word line) is formed on a first surface of the front end of line structure. A backside structure is formed on a second surface of the front end of line structure opposite the first surface. The backside structure includes a backside metallization layer (bit line) in direct contact with the one or more programmed backside vias.

    BACKSIDE PROGRAMMABLE GATE ARRAY
    44.
    发明公开
    BACKSIDE PROGRAMMABLE GATE ARRAY 审中-公开

    公开(公告)号：US20240162231A1

    公开(公告)日：2024-05-16

    申请号：US18054160

    申请日：2022-11-10

    Applicant: International Business Machines Corporation

    Inventor： Albert M. Chu ,  Brent A. Anderson ,  Junli Wang ,  Albert M. Young ,  Ruilong Xie ,  Carl Radens

    IPC: H01L27/118

    CPC classification number: H01L27/11807 ,  H01L2027/11875 ,  H01L2027/11881

    Abstract: Embodiments of the present invention are directed to processing methods and resulting structures for integrated circuits having backside programmable gate arrays. In a non-limiting embodiment, a front end of line structure having an array of transistors is formed such that each transistor of the array of transistors includes one or more placeholder backside vias. A first portion of the backside vias defines one or more placeholder backside vias and a second portion of the one or more backside vias defines one or more programmed backside vias. A back end of line structure is formed on a first surface of the front end of line structure. A backside structure is formed on a second surface of the front end of line structure opposite the first surface. The backside structure includes a backside metallization layer in direct contact with the one or more programmed backside vias.

    Stacked FET SRAM
    47.
    发明授权
    Stacked FET SRAM 有权

    公开(公告)号：US11895818B2

    公开(公告)日：2024-02-06

    申请号：US17660640

    申请日：2022-04-26

    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

    Inventor： Ruilong Xie ,  Carl Radens ,  Junli Wang ,  Ravikumar Ramachandran ,  Julien Frougier ,  Dechao Guo

    IPC: H10B10/00 ,  G11C11/412

    CPC classification number: H10B10/12 ,  G11C11/412

    Abstract: Embodiments of present invention provide a SRAM device. The SRAM device includes a first, a second, and a third SRAM cell each having a first and a second pass-gate (PG) transistor, wherein the second PG transistor of the second SRAM cell and the first PG transistor of the first SRAM cell are stacked in a first PG transistor cell, and the first PG transistor of the third SRAM cell and the second PG transistor of the first SRAM cell are stacked in a second PG transistor cell. The first and second PG transistors of the first SRAM cell may be stacked on top of, or underneath, the second PG transistor of the second SRAM cell and/or the first PG transistor of the third SRAM cell.

    BRIDGE CELL PHASE CHANGE MEMORY
    50.
    发明公开
    BRIDGE CELL PHASE CHANGE MEMORY 审中-公开

    公开(公告)号：US20230200266A1

    公开(公告)日：2023-06-22

    申请号：US17552498

    申请日：2021-12-16

    Applicant: International Business Machines Corporation

    Inventor： Ruilong Xie ,  Carl Radens ,  Juntao Li ,  Kangguo Cheng

    IPC: H01L45/00

    CPC classification number: H01L45/06 ,  H01L45/1226 ,  H01L45/1608 ,  H01L45/1675 ,  H01L45/144

    Abstract: A phase change bridge memory cell includes: a first interlevel dielectric layer; a first electrode and a second electrode disposed in the first interlevel dielectric layer and separated by a portion of the first interlevel dielectric layer; an interlevel dielectric pillar on the portion of the first interlevel dielectric layer; a first phase change material on the interlevel dielectric pillar; and a second phase change material including two areas on opposite sides of the interlevel dielectric pillar and electrically connected by the first phase change material, wherein the second phase change material is connected to the first electrode and the second electrode.

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