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公开(公告)号：US20220069027A1
公开(公告)日：2022-03-03
申请号：US17355739
申请日：2021-06-23
Applicant: BOE TECHNOLOGY GROUP CO., LTD.
Inventor： Hongli WANG , Chang LUO , Lei CHEN , Kening ZHENG , Chen XU
IPC: H01L27/32 , H01L51/52 , G09G3/20 , G09G3/3225
Abstract: A display panel and a display device are provided. The display panel includes a first color sub-pixels and a second color sub-pixel. The first color sub-pixel includes a first effective light emitting region, the second color sub-pixel includes a second effective light emitting region, an area of the second effective light emitting region is smaller than that of the first effective light emitting region. The first color sub-pixel includes a first color light emitting layer, the second color sub-pixel includes a second color light emitting layer, an area ratio between orthographic projections of the first color light emitting layer and the first effective light emitting region on the base substrate is less than an area ratio between orthographic projections of the second color light emitting layer and the second effective light emitting region on the base substrate.
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公开(公告)号：US20210183982A1
公开(公告)日：2021-06-17
申请号：US16960729
申请日：2019-08-23
Applicant: BOE TECHNOLOGY GROUP CO., LTD.
Inventor： Dachao LI , Shengji YANG , Chen XU
IPC: H01L27/32
Abstract: A display device and a manufacturing method thereof are disclosed. The display device includes a base substrate and at least one pixel circuit provided on the base substrate. The pixel circuit includes a driving transistor, a first transistor, and a second transistor; the base substrate includes a semiconductor body that can be doped, and a first conductive layer and a second conductive layer that are on the semiconductor body; the first transistor includes a first doped region in contact with the first electrode of the first transistor, and a second doped region in contact with a second electrode of the first transistor, and the first doped region of the first transistor and the second doped region of the first transistor are spaced apart from each other, have a same doping type, and are both in the semiconductor body.
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公开(公告)号：US20190148319A1
公开(公告)日：2019-05-16
申请号：US16122035
申请日：2018-09-05
Applicant: BOE Technology Group Co., Ltd.
Inventor： Liqiang CHEN , Paoming TSAI , Jianwei LI , Chen XU
Abstract: The disclosure relates to the field of display technologies and particularly to a chip, a flexible display panel and a display device. The chip includes a body and a plurality of connection terminals arranged on a surface of the body, where each connection terminal is provided with a stress concentration resisting structure for preventing from producing the stress concentration phenomenon.
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公开(公告)号：US20250098299A1
公开(公告)日：2025-03-20
申请号：US18292969
申请日：2022-09-26
Inventor： Guodong YANG , Xiaoyuan WANG , Hui GUO , Chen XU , Bin WAN , Junming CHEN , Yan LIU , Xun PU , Yuanyuan ZHU
IPC: H01L27/12
Abstract: Provided is an array substrate. The array substrate includes a substrate, comprising a display region and a peripheral region surrounding the display region, the peripheral region at least including a gate-driver-on-array (GOA) region extending in a first direction; a plurality of thin film transistors, the plurality of thin film transistors being disposed at least in the GOA region; and a plurality of first patterns, wherein the plurality of first patterns are disposed at least on one side of the GOA region, the plurality of first patterns are spaced apart from the GOA region in the first direction, and a plurality of first patterns disposed on a same side of the GOA region are arranged in an array.
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公开(公告)号：US20250093705A1
公开(公告)日：2025-03-20
申请号：US18292110
申请日：2022-10-31
Inventor： Bin WAN , Xiaoyuan WANG , Hui GUO , Chen XU , Guodong YANG , Junming CHEN , Yan LIU , Xun PU , Yuanyuan ZHU , Zhongshan WU , Dan LEI
IPC: G02F1/1339 , G02F1/1333 , G02F1/1345 , G09G3/36
Abstract: A display substrate is provided to include: a first base substrate including a sealing region and a display port region, wherein at least one first connection region and at least one second connection region are in the display port region, a first overlapping region is formed between the second and first connection regions; first and second connection terminals in the first and second connection regions, respectively; and a planarization layer including at least one first trench and at least one second trench corresponding to the first and second connection regions therein, respectively; orthographic projections of bottoms of first and second trenches on the first base substrate cover corresponding first and second connection regions, respectively; the planarization layer includes: a first pattern corresponding to the first overlapping region; orthographic projections of the first pattern and its corresponding first overlapping region on the first base substrate overlap with each other.
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Patent Agency Ranking
公开(公告)号：US20250031447A1
公开(公告)日：2025-01-23
申请号：US18279205
申请日：2022-10-31
Applicant: BOE Technology Group Co., Ltd.
Inventor： Zhengliang LI , Guangcai YUAN , Ce NING , Zhonghao HUANG , Zhixiang ZOU , Zhangtao WANG , Jie HUANG , Nianqi YAO , Jiayu HE , Hehe HU , Feifei LI , Kun ZHAO , Chen XU , Hui GUO
Abstract: A display substrate, including: a base substrate; and a metal conductive layer, located at a side of the base substrate, and including a core conductive layer and a functional conductive layer laminated along a direction away from the base substrate; a material of the core conductive layer includes a conductive metal material; a material of the functional conductive layer includes a first diffusion barrier metal material and a first adhesion force enhancing metal material, wherein the first diffusion barrier metal material is configured to block diffusion of the conductive metal material, and the first adhesion force enhancing metal material is configured to enhance an adhesion force between the functional conductive layer and a photoresist used in a patterning process of the functional conductive layer; a surface energy of any of first adhesion force enhancing metal materials is less than or equal to 325 mJ/m2.
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公开(公告)号：US20250023246A1
公开(公告)日：2025-01-16
申请号：US18280144
申请日：2022-10-26
Abstract: A holographic antenna includes first and second dielectric substrates, a waveguide structure, a radiation layer, a plurality of switch units and a plurality of isolation components; the first dielectric substrate is on a waveguide port of the waveguide structure; the radiation layer is on a side of the first dielectric substrate away from the waveguide structure, and has a plurality of slits; the second dielectric substrate is on a side of the radiation layer away from the first dielectric substrate; the switch units and the isolation components are between the second dielectric substrate and the radiation layer; orthographic projections of each isolation component and each slit on the first dielectric substrate are first and second patterns, respectively; at least one first pattern is between two adjacent second patterns, and a first distance is between the second pattern and the first pattern closest to the second pattern.
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公开(公告)号：US20240312419A1
公开(公告)日：2024-09-19
申请号：US18620521
申请日：2024-03-28
Applicant: BOE TECHNOLOGY GROUP CO., LTD.
Inventor： Xing YAO , Chen XU , Jingquan WANG , Xinyin WU
IPC: G09G3/3266 , H10K59/126 , H10K59/131
CPC classification number: G09G3/3266 , H10K59/126 , H10K59/131 , G09G2300/0426 , G09G2310/0286
Abstract: A display substrate is provided. The display substrate includes a base substrate including a display region and a peripheral region, a gate scan driving circuit, a light-emitting control scan driving circuit, a first power line, a first planarization layer, a second planarization layer and a first shielding layer and a second shielding layer. The first planarization layer and the second planarization layer further include an open slot. The second shielding layer extends from a region corresponding to the light-emitting control scan driving circuit to a region corresponding to the gate scan driving circuit and covers the open slot. In an area where the second shielding layer is close to the open slot, an orthographic projection of the second shielding layer covering the open slot on the base substrate at least overlaps with an orthographic projection of the first shielding layer on the base substrate.
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公开(公告)号：US20240250177A1
公开(公告)日：2024-07-25
申请号：US18014269
申请日：2022-03-31
Applicant: BOE TECHNOLOGY GROUP CO., LTD.
Inventor： Dapeng XUE , Lizhong WANG , Shuilang DONG , Hehe HU , Nianqi YAO , Guangcai YUAN , Ce NING , Zhengliang LI , Dongfang WANG , Liping LEI , Chen XU , Jie HUANG
IPC: H01L29/786 , H01L27/12 , H01L29/417
CPC classification number: H01L29/7869 , H01L27/1225 , H01L29/41733 , H01L29/78696
Abstract: A metal oxide thin film transistor is provided, which includes a metal oxide semiconductor layer, including a first semiconductor layer and a second semiconductor layer, the carrier mobility of the first semiconductor layer is higher than that of the second semiconductor layer; the metal oxide semiconductor layer includes a lower surface, an upper surface and a lateral surface, the source electrode is in contact with the lateral surface and the upper surface; the region where the lateral surface contacts the source electrode or the drain electrode includes a first contact region and a second contact region; which have the shape: a first angle between the lower surface of the metal oxide semiconductor layer and the lateral surface of the first contact region is larger than a second angle between the lower surface of the metal oxide semiconductor layer and the lateral surface of the second contact region.
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50.发明公开公开(公告)号：US20240212639A1
公开(公告)日：2024-06-27
申请号：US17913798
申请日：2021-09-24
Applicant: BOE Technology Group Co., Ltd.
Inventor： Shuilang DONG , Ce NING , Guangcai YUAN , Hehe HU , Lizhong WANG , Nianqi YAO , Dapeng XUE , Liping LEI , Chen XU , Dongfang WANG , Zhengliang LI
IPC: G09G3/36
CPC classification number: G09G3/36 , G09G2310/0286 , G09G2310/061 , G09G2330/021
Abstract: Voltage providing unit, voltage providing method, display driving module and display device are provided. The voltage providing unit, applied to a display panel, is configured to provide a control voltage signal for a driving circuit, and the voltage providing unit includes a buck circuit and a first electrical level converting circuit. The buck circuit is configured to receive a first voltage signal and perform a buck operation on the first voltage signal to obtain a second voltage signal; and the first electrical level converting circuit is connected to the buck circuit, and is configured to receive an input control voltage, a third voltage signal and the second voltage signal, and to generate the control voltage signal in accordance with the input control voltage, the third voltage signal and the second voltage signal, a voltage value of the control voltage signal is less than a predetermined voltage value.
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