公开(公告)号：US12117320B2

公开(公告)日：2024-10-15

申请号：US17366459

申请日：2021-07-02

Applicant: Apple Inc.

Inventor： Brijesh Tripathi ,  Shane J. Keil ,  Manu Gulati ,  Jung Wook Cho ,  Erik P. Machnicki ,  Gilbert H. Herbeck ,  Timothy J. Millet ,  Joshua P. de Cesare ,  Anand Dalal ,  Michael F. Culbert

IPC: G01D9/00 ,  A61G3/06 ,  B60P1/43 ,  G06F1/3206 ,  G06F1/3287 ,  G06F1/3293 ,  G06F13/16

CPC classification number: G01D9/00 ,  A61G3/061 ,  B60P1/433 ,  G06F1/3206 ,  G06F1/3287 ,  G06F1/3293 ,  G06F13/1689 ,  Y02D10/00 ,  Y02D30/50

Abstract: In an embodiment, a system on a chip (SOC) includes a component that remains powered when a central processing unit (CPU) processor and a memory controller of the SOC are powered off. The component may include a sensor capture unit to capture audio samples from an audio detector circuit and write them to a memory of the component. A processor of the component may be configured to search the audio samples for a predetermined pattern during a time when the CPU processor and the memory controller are powered down. In some embodiments, based on the audio samples filling to a threshold level in the memory of the component and a lack of detection of the predetermined pattern, the component is configured to wake up the memory controller and a path to the memory controller in order to write the audio sample to a memory controlled by the memory controller.

公开(公告)号：US11049503B2

公开(公告)日：2021-06-29

申请号：US16786127

申请日：2020-02-10

Applicant: Apple Inc.

Inventor： Timothy J. Millet ,  Manu Gulati ,  Michael F. Culbert

IPC: G10L15/22 ,  G10L15/28 ,  G06F3/16 ,  G06F1/3228 ,  G06F1/3287 ,  G06F1/32 ,  G10L15/08 ,  G10L25/48

Abstract: In an embodiment, an integrated circuit may include one or more CPUs, a memory controller, and a circuit configured to remain powered on when the rest of the SOC is powered down. The circuit may be configured to receive audio samples from a microphone, and match those audio samples against a predetermined pattern to detect a possible command from a user of the device that includes the SOC. In response to detecting the predetermined pattern, the circuit may cause the memory controller to power up so that audio samples may be stored in the memory to which the memory controller is coupled. The circuit may also cause the CPUs to be powered on and initialized, and the operating system (OS) may boot. During the time that the CPUs are initializing and the OS is booting, the circuit and the memory may be capturing the audio samples.

公开(公告)号：US20190378514A1

公开(公告)日：2019-12-12

申请号：US16546574

申请日：2019-08-21

Applicant: Apple Inc.

Inventor： Timothy J. Millet ,  Manu Gulati ,  Michael F. Culbert

IPC: G10L15/28 ,  G06F1/3228 ,  G06F1/3287 ,  G06F1/32 ,  G10L15/22 ,  G06F3/16

Abstract: In an embodiment, an integrated circuit may include one or more CPUs, a memory controller, and a circuit configured to remain powered on when the rest of the SOC is powered down. The circuit may be configured to receive audio samples from a microphone, and match those audio samples against a predetermined pattern to detect a possible command from a user of the device that includes the SOC. In response to detecting the predetermined pattern, the circuit may cause the memory controller to power up so that audio samples may be stored in the memory to which the memory controller is coupled. The circuit may also cause the CPUs to be powered on and initialized, and the operating system (OS) may boot. During the time that the CPUs are initializing and the OS is booting, the circuit and the memory may be capturing the audio samples.

公开(公告)号：US20180350369A1

公开(公告)日：2018-12-06

申请号：US16101603

申请日：2018-08-13

Applicant: Apple Inc.

Inventor： Timothy J. Millet ,  Manu Gulati ,  Michael F. Culbert

IPC: G10L15/28 ,  G06F3/16 ,  G06F1/32 ,  G10L15/22 ,  G10L25/48 ,  G10L15/08

CPC classification number: G10L15/28 ,  G06F1/32 ,  G06F1/3228 ,  G06F1/3287 ,  G06F3/165 ,  G10L15/22 ,  G10L25/48 ,  G10L2015/088 ,  Y02D10/171

Abstract: In an embodiment, an integrated circuit may include one or more CPUs, a memory controller, and a circuit configured to remain powered on when the rest of the SOC is powered down. The circuit may be configured to receive audio samples from a microphone, and match those audio samples against a predetermined pattern to detect a possible command from a user of the device that includes the SOC. In response to detecting the predetermined pattern, the circuit may cause the memory controller to power up so that audio samples may be stored in the memory to which the memory controller is coupled. The circuit may also cause the CPUs to be powered on and initialized, and the operating system (OS) may boot. During the time that the CPUs are initializing and the OS is booting, the circuit and the memory may be capturing the audio samples.

公开(公告)号：US20180313673A1

公开(公告)日：2018-11-01

申请号：US16019087

申请日：2018-06-26

Applicant: Apple Inc.

Inventor： Brijesh Tripathi ,  Shane J. Keil ,  Manu Gulati ,  Jung Wook Cho ,  Erik P. Machnicki ,  Gilbert H. Herbeck ,  Timothy J. Millet ,  Joshua P. de Cesare ,  Anand Dalal

IPC: G01D9/00 ,  G06F1/32 ,  G06F13/16

CPC classification number: G01D9/00 ,  G06F1/3206 ,  G06F1/3287 ,  G06F1/3293 ,  G06F13/1689 ,  Y02D10/122 ,  Y02D10/171 ,  Y02D50/20

Abstract: In an embodiment, a system on a chip (SOC) includes a component that remains powered when the remainder of the SOC is powered off. The component may include a sensor capture unit to capture data from various device sensors, and may filter the captured sensor data. Responsive to the filtering, the component may wake up the remainder of the SOC to permit the processing. The component may store programmable configuration data, matching the state at the time the SOC was most recently powered down, for the other components of the SOC, in order to reprogram them after wakeup. In some embodiments, the component may be configured to wake up the memory controller within the SOC and the path to the memory controller, in order to write the data to memory. The remainder of the SOC may remain powered down.

公开(公告)号：US10102607B2

公开(公告)日：2018-10-16

申请号：US15692469

申请日：2017-08-31

Applicant: Apple Inc.

Inventor： Timothy J. Millet ,  Manu Gulati ,  Arthur L. Spence ,  Gurjeet S. Saund ,  Robert P. Esser

IPC: G06T1/20 ,  G06F9/52 ,  G06F9/48 ,  G06T1/60 ,  G09G5/36 ,  G09G5/00

Abstract: One embodiment may include media circuits, an application processor, a direct memory access circuit (DMA), and a media managing circuit. The application processor may issue media commands into a queue. The media managing circuit may retrieve a first media command, set the DMA to copy data associated with the first media command to the first media circuit, and send the first media command to the first media circuit. While the first media command is being executed, the media managing circuit may also retrieve a second media command, determine that the second media command utilizes data that is dependent on a completion of the first media command, and set the DMA to copy data from the first media circuit to the second media circuit. After the first media command has been completed, the media managing circuit may also send the second media command to the second media circuit.

公开(公告)号：US10038845B2

公开(公告)日：2018-07-31

申请号：US15414866

申请日：2017-01-25

Applicant: Apple Inc.

Inventor： D. Amnon Silverstein ,  Shun Wai Go ,  Suk Hwan Lim ,  Timothy J. Millet ,  Ting Chen ,  Bin Ni

IPC: H04N5/225 ,  H04N5/232 ,  H04N7/01 ,  H04N9/87 ,  H04N1/21

CPC classification number: H04N5/23245 ,  H04N1/212 ,  H04N5/23216 ,  H04N5/23232 ,  H04N5/23293 ,  H04N7/0122 ,  H04N9/87

Abstract: In an embodiment, an electronic device may be configured to capture still frames during video capture, but may capture the still frames in the 4×3 aspect ratio and at higher resolution than the 16×9 aspect ratio video frames. The device may interleave high resolution, 4×3 frames and lower resolution 16×9 frames in the video sequence, and may capture the nearest higher resolution, 4×3 frame when the user indicates the capture of a still frame. Alternatively, the device may display 16×9 frames in the video sequence, and then expand to 4×3 frames when a shutter button is pressed. The device may capture the still frame and return to the 16×9 video frames responsive to a release of the shutter button.

公开(公告)号：US20170365034A1

公开(公告)日：2017-12-21

申请号：US15692469

申请日：2017-08-31

Applicant: Apple Inc.

Inventor： Timothy J. Millet ,  Manu Gulati ,  Arthur L. Spence ,  Gurjeet S. Saund ,  Robert P. Esser

IPC: G06T1/20 ,  G06F9/52 ,  G06F9/48 ,  G06T1/60 ,  G09G5/00 ,  G09G5/36

CPC classification number: G06T1/20 ,  G06F9/4893 ,  G06F9/52 ,  G06T1/60 ,  G09G5/001 ,  G09G5/363 ,  G09G2360/08 ,  Y02D10/24

Abstract: One embodiment may include media circuits, an application processor, a direct memory access circuit (DMA), and a media managing circuit. The application processor may issue media commands into a queue. The media managing circuit may retrieve a first media command, set the DMA to copy data associated with the first media command to the first media circuit, and send the first media command to the first media circuit. While the first media command is being executed, the media managing circuit may also retrieve a second media command, determine that the second media command utilizes data that is dependent on a completion of the first media command, and set the DMA to copy data from the first media circuit to the second media circuit. After the first media command has been completed, the media managing circuit may also send the second media command to the second media circuit.

公开(公告)号：US09762919B2

公开(公告)日：2017-09-12

申请号：US14472119

申请日：2014-08-28

Applicant: Apple Inc.

Inventor： Guy Cote ,  Joseph P. Bratt ,  Timothy J. Millet ,  Shing I. Kong ,  Joseph J. Cheng

IPC: H04N19/127 ,  H04N19/176 ,  H04N19/186 ,  H04N19/423 ,  H04N19/433 ,  G06F12/00 ,  H04N19/42 ,  H04N19/172 ,  G06T1/60

CPC classification number: H04N19/186 ,  G06F12/00 ,  G06F12/0207 ,  G06F12/0862 ,  G06F12/121 ,  G06F2212/1024 ,  G06F2212/455 ,  G06F2212/6024 ,  G06F2212/6026 ,  G06T1/60 ,  H04N19/127 ,  H04N19/172 ,  H04N19/176 ,  H04N19/423 ,  H04N19/433 ,  H04N19/439

Abstract: Methods and apparatus for caching reference data in a block processing pipeline. A cache may be implemented to which reference data corresponding to motion vectors for blocks being processed in the pipeline may be prefetched from memory. Prefetches for the motion vectors may be initiated one or more stages prior to a processing stage. Cache tags for the cache may be defined by the motion vectors. When a motion vector is received, the tags can be checked to determine if there are cache block(s) corresponding to the vector (cache hits) in the cache. Upon a cache miss, a cache block in the cache is selected according to a replacement policy, the respective tag is updated, and a prefetch (e.g., via DMA) for the respective reference data is issued.

公开(公告)号：US09727505B2

公开(公告)日：2017-08-08

申请号：US14709336

申请日：2015-05-11

Applicant: Apple Inc.

Inventor： David G. Conroy ,  Timothy J. Millet ,  Joseph P. Bratt

IPC: G06F13/28 ,  G06F13/34 ,  G06F1/12 ,  G06F1/32 ,  G06F13/16

CPC classification number: G06F13/34 ,  G06F1/12 ,  G06F1/3203 ,  G06F1/324 ,  G06F1/3253 ,  G06F1/3287 ,  G06F13/1673 ,  G06F13/28 ,  Y02D10/126 ,  Y02D10/151 ,  Y02D10/171

Abstract: A method and system is disclosed for accessing I/O and memory devices utilizing a DMA controller. Each device may be connected to the DMA controller through an individual channel. Clocking circuitry in the DMA may allow the DMA controller to send signals to each device at a prescribed frequency. Furthermore, the DMA controller is capable of activating and deactivating a channel clock, used in sending signals to the devices, based on the operational status of the individual devices. The DMA controller is also capable of tuning the channel clock dependant on the capabilities of any active devices. In this manner, the amount of bandwidth used during a DMA data transfer can be tailored to the specific requirements of the devices involved with the data transfer.