公开(公告)号：US10031000B2

公开(公告)日：2018-07-24

申请号：US14458885

申请日：2014-08-13

Applicant: Apple Inc.

Inventor： Brijesh Tripathi ,  Shane J. Keil ,  Manu Gulati ,  Jung Wook Cho ,  Erik P. Machnicki ,  Gilbert H. Herbeck ,  Timothy J. Millet ,  Joshua P. de Cesare ,  Anand Dalal

IPC: G06F1/32 ,  G01D9/00 ,  G06F13/16

CPC classification number: G01D9/00 ,  G06F1/3206 ,  G06F1/3287 ,  G06F1/3293 ,  G06F13/1689 ,  Y02D10/122 ,  Y02D10/171 ,  Y02D50/20

Abstract: In an embodiment, a system on a chip (SOC) includes a component that remains powered when the remainder of the SOC is powered off. The component may include a sensor capture unit to capture data from various device sensors, and may filter the captured sensor data. Responsive to the filtering, the component may wake up the remainder of the SOC to permit the processing. The component may store programmable configuration data, matching the state at the time the SOC was most recently powered down, for the other components of the SOC, in order to reprogram them after wakeup. In some embodiments, the component may be configured to wake up the memory controller within the SOC and the path to the memory controller, in order to write the data to memory. The remainder of the SOC may remain powered down.

公开(公告)号：US09959124B1

公开(公告)日：2018-05-01

申请号：US14498428

申请日：2014-09-26

Applicant: Apple Inc.

Inventor： Gilbert H. Herbeck ,  Manu Gulati ,  Erik P. Machnicki ,  Timothy R. Paaske

IPC: G06F1/32 ,  G06F9/44

CPC classification number: G06F9/4401 ,  G06F1/3287 ,  G06F9/4411 ,  G06F9/4418

Abstract: In an embodiment, a system includes a functional unit that remains powered when the remainder of the system is powered off. The functional unit may, in response to a transition from a first power state to a second power state, retrieve configuration information from a read-only memory. In some embodiments, may be configured to store at least a portion of the configured information in a secure portion of a memory included in the functional unit and then lock the secure portion of the memory. The functional unit may then complete the transition to the second power state.

公开(公告)号：US09864399B2

公开(公告)日：2018-01-09

申请号：US14965073

申请日：2015-12-10

Applicant: Apple Inc.

Inventor： Shu-Yi Yu ,  Erik P. Machnicki ,  Gilbert H. Herbeck ,  Kiran B. Kattel ,  Manu Gulati

IPC: G06F1/12

CPC classification number: G06F1/12 ,  G06F1/14

Abstract: In an embodiment, an integrated circuit such as an SOC (or even a discrete chip system) includes one or more local timebases in various locations. The timebases may be incremented based on a high frequency local clock that may be subject to variation during use due. Periodically, based on a lower frequency clock that is subject to less variation, the local timebases may be synchronized to the correct time, using hardware circuitry. In particular, the correct timebase value for the next synchronization may be transmitted to each local timebase, and the control circuit for the local timebase may be configured to saturate the local timebase at the correct value if the local timebase reaches the correct value before the synchronization occurs. Similarly, if the synchronization occurs and the local timebase has not reached the correct value, the control circuit may be configured to load the correct timebase value.

公开(公告)号：US09658634B2

公开(公告)日：2017-05-23

申请号：US14673326

申请日：2015-03-30

Applicant: Apple Inc.

Inventor： Brijesh Tripathi ,  Eric G. Smith ,  Erik P. Machnicki ,  Jung Wook Cho ,  Khaled M. Alashmouny ,  Kiran B. Kattel ,  Vijay M. Bettada ,  Bo Yang ,  Wenlong Wei

IPC: G06F1/00 ,  G05F3/02 ,  G06F1/32

CPC classification number: G05F3/02 ,  G06F1/324 ,  G06F1/3296

Abstract: An under voltage detection circuit and method of operating an IC including the same is disclosed. In one embodiment, an IC includes an under voltage protection circuit having first and second comparators configured to compare a supply voltage to first and second voltage thresholds, respectively, with the second voltage threshold being greater than the first. A logic circuit is coupled to receive signals from the first and second comparators. During operation in a high performance state by a corresponding functional circuit, the logic circuit is configured to cause assertion of a throttling signal responsive to an indication that the supply voltage has fallen below the first threshold. A clock signal provided to the functional circuit may be throttled responsive to the indication. If the supply voltage subsequently rises to a level above the second threshold, the throttling signal may be de-asserted.

公开(公告)号：US20160091954A1

公开(公告)日：2016-03-31

申请号：US14499807

申请日：2014-09-29

Applicant: Apple Inc.

Inventor： Cyril de la Cropte de Chanterac ,  Manu Gulati ,  Erik P. Machnicki ,  Keith Cox ,  Timothy J. Millet

IPC: G06F1/32

CPC classification number: G06F1/3234 ,  G06F1/3203 ,  G06F1/3206 ,  G06F1/324 ,  G06F1/3243 ,  G06F1/3296 ,  Y02D10/126 ,  Y02D10/152 ,  Y02D10/172

Abstract: Embodiments of a method that allow the adjustment of performance settings of a computing system are disclosed. One or more functional units may include multiple monitor circuits, each of which may be configured to monitor a given operational parameter of a corresponding functional unit. Upon detection of an event related to a monitored operational parameter, a monitor circuit may generate an interrupt. In response to the interrupt a processor may adjust one or more performance settings of the computing system.

Abstract translation: 公开了允许调整计算系统的性能设置的方法的实施例。 一个或多个功能单元可以包括多个监视器电路，每个监视器电路可以被配置为监视对应功能单元的给定操作参数。 在检测到与所监视的操作参数有关的事件时，监视器电路可产生中断。 响应于中断，处理器可以调整计算系统的一个或多个性能设置。

公开(公告)号：US09043632B2

公开(公告)日：2015-05-26

申请号：US13626522

申请日：2012-09-25

Applicant: Apple Inc.

Inventor： Erik P. Machnicki ,  Manu Gulati ,  Josh P. de Cesare

IPC: G06F1/26 ,  G06F1/32 ,  G06F1/00 ,  G06F7/04 ,  H04N7/16 ,  G06F11/00 ,  G06F21/57 ,  G06F21/74 ,  G06F21/70 ,  G06F21/60 ,  G06F21/71

CPC classification number: G06F1/26 ,  G06F1/32 ,  G06F1/3206 ,  G06F1/3234 ,  G06F1/3237 ,  G06F1/3287 ,  G06F21/575 ,  G06F21/602 ,  G06F21/70 ,  G06F21/71 ,  G06F21/74

Abstract: An SOC implements a security enclave processor (SEP). The SEP may include a processor and one or more security peripherals. The SEP may be isolated from the rest of the SOC (e.g. one or more central processing units (CPUs) in the SOC, or application processors (APs) in the SOC). Access to the SEP may be strictly controlled by hardware. For example, a mechanism in which the CPUs/APs can only access a mailbox location in the SEP is described. The CPU/AP may write a message to the mailbox, which the SEP may read and respond to. The SEP may include one or more of the following in some embodiments: secure key management using wrapping keys, SEP control of boot and/or power management, and separate trust zones in memory.

Abstract translation: SOC实现安全飞地处理器（SEP）。 SEP可以包括处理器和一个或多个安全外设。 SEP可以与SOC的其余部分隔离（例如SOC中的一个或多个中央处理单元（CPU），或SOC中的应用处理器（AP））。 对SEP的访问可以由硬件严格控制。 例如，描述了CPU / AP仅能访问SEP中的邮箱位置的机制。 CPU / AP可以向邮箱写入消息，SEP可以读取并响应。 在一些实施例中，SEP可以包括以下一个或多个：使用包裹密钥的安全密钥管理，引导和/或电源管理的SEP控制以及存储器中的单独的信任区域。

公开(公告)号：US08786332B1

公开(公告)日：2014-07-22

申请号：US13744004

申请日：2013-01-17

Applicant: Apple Inc.

Inventor： Erik P. Machnicki ,  David S. Warren ,  Shane J. Keil ,  Sukalpa Biswas

IPC: H03L7/00 ,  G06F1/24

CPC classification number: G06F1/24 ,  G06F1/10 ,  H03L5/00

Abstract: A clock divider may provide a lower speed clock to a logic block portion, but during reset, the clock divider may not operate properly, causing the logic block portion to be reset at a clock frequency greater than the frequency for which that logic was designed. However, an extended reset may be employed in which the clock divider is reset normally first before the logic block portion, allowing that logic to be reset according to the divided clock (e.g., rather than a higher speed clock). An asynchronous reset may also be employed in which one or more clock dividers first emerge from reset before being provided with a (synchronized) high speed clock signal, causing the clock dividers to be in phase with each other. This may enable communication between different areas of an IC that might not otherwise be in proper phase with each other.

Abstract translation: 时钟分频器可以向逻辑块部分提供较低速度的时钟，但是在复位期间，时钟分频器可能无法正常工作，导致逻辑块部分在大于设计该逻辑的频率的时钟频率下复位。 然而，可以采用扩展复位，其中时钟分频器首先在逻辑块部分之前正常复位，从而允许根据分频时钟（例如，而不是更高速度的时钟）来复位该逻辑。 还可以采用异步复位，其中一个或多个时钟分频器首先在被提供有（同步的）高速时钟信号之前从复位中出现，使得时钟分频器彼此同相。 这可以使IC之间的不同区域之间的通信可能不会彼此正确相位。

公开(公告)号：US20140197870A1

公开(公告)日：2014-07-17

申请号：US13744004

申请日：2013-01-17

Applicant: APPLE INC.

Inventor： Erik P. Machnicki ,  David S. Warren ,  Shane J. Keil ,  Sukalpa Biswas

IPC: H03L5/00

CPC classification number: G06F1/24 ,  G06F1/10 ,  H03L5/00

Abstract: A clock divider may provide a lower speed clock to a logic block portion, but during reset, the clock divider may not operate properly, causing the logic block portion to be reset at a clock frequency greater than the frequency for which that logic was designed. However, an extended reset may be employed in which the clock divider is reset normally first before the logic block portion, allowing that logic to be reset according to the divided clock (e.g., rather than a higher speed clock). An asynchronous reset may also be employed in which one or more clock dividers first emerge from reset before being provided with a (synchronized) high speed clock signal, causing the clock dividers to be in phase with each other. This may enable communication between different areas of an IC that might not otherwise be in proper phase with each other.

Abstract translation: 时钟分频器可以向逻辑块部分提供较低速度的时钟，但是在复位期间，时钟分频器可能无法正常工作，导致逻辑块部分在大于设计该逻辑的频率的时钟频率下复位。 然而，可以采用扩展复位，其中时钟分频器首先在逻辑块部分之前正常复位，从而允许根据分频时钟（例如，而不是更高速度的时钟）来复位该逻辑。 还可以采用异步复位，其中一个或多个时钟分频器首先在被提供有（同步的）高速时钟信号之前从复位中出现，使得时钟分频器彼此同相。 这可以使IC之间的不同区域之间的通信可能不会彼此正确相位。

公开(公告)号：US20140173307A1

公开(公告)日：2014-06-19

申请号：US13719535

申请日：2012-12-19

Applicant: APPLE INC.

Inventor： Erik P. Machnicki ,  Gurjeet S. Saund ,  Munetoshi Fukami ,  Shane J. Keil ,  Chaitanya Kosaraju ,  Erdem Guleyupoglu ,  Jason M. Kassoff ,  Kevin C. Wong

IPC: G06F1/32

CPC classification number: G06F1/3287 ,  G06F1/3206 ,  G06F1/3246 ,  G06F1/329 ,  G06F1/3293 ,  Y02D10/24 ,  Y02D50/20

Abstract: A method and apparatus for interfacing dynamic hardware power managed blocks and software power managed blocks is disclosed. In one embodiment, and integrated circuit (IC) may include a number of power manageable functional units. The functional units maybe power managed through hardware, software, or both. Each of the functional units may be coupled to at least one other functional unit through a direct communications link. A link state machine may monitor each of the communications links between functional units, and may broadcast indications of link availability to the functional units coupled to the link. Responsive to a software request to shut down a given link, or a hardware initiated shutdown of one of the functional units coupled to the link, the link state machine may broadcast and indication that the link is unavailable.

Abstract translation: 公开了用于接口动态硬件功率管理块和软件功率管理块的方法和装置。 在一个实施例中，集成电路（IC）可以包括多个功率可管理的功能单元。 功能单元可以通过硬件，软件或两者进行功率管理。 每个功能单元可以通过直接通信链路耦合到至少一个其它功能单元。 链路状态机可以监视功能单元之间的每个通信链路，并且可以将链路可用性的指示广播到耦合到链路的功能单元。 响应于关闭给定链路的软件请求或耦合到链路的功能单元之一的硬件启动关机，链路状态机可以广播并指示链路不可用。

公开(公告)号：US20140108688A1

公开(公告)日：2014-04-17

申请号：US13653151

申请日：2012-10-16

Applicant: APPLE INC.

Inventor： Manu Gulati ,  Erik P. Machnicki ,  Deniz Balkan

IPC: G06F13/24

CPC classification number: G06F13/24 ,  G06F13/26 ,  Y02D10/14

Abstract: In an embodiment, a system includes at least one peripheral device, an interrupt controller, a memory controller, at least one CPU, and an interrupt message circuit coupled to the peripheral device. The interrupt message circuit may be coupled to receive the interrupt signal from the peripheral device, and may be configured to generate an interrupt message for transmission on a communication fabric. In some embodiments, there may be multiple peripherals which have independent paths through the fabric for memory operations to the memory controller. Each such peripheral may be coupled to an instance of the interrupt message circuit. In an embodiment, the interrupt is level sensitive. The interrupt message circuit may be configured to transmit interrupt set messages an interrupt clear messages to the interrupt controller, to indicate the levels.

Abstract translation: 在一个实施例中，系统包括耦合到外围设备的至少一个外围设备，中断控制器，存储器控制器，至少一个CPU以及中断消息电路。 中断消息电路可以被耦合以从外围设备接收中断信号，并且可以被配置为生成用于在通信结构上传输的中断消息。 在一些实施例中，可以存在多个外围设备，其具有通过该结构的独立路径，用于存储器操作到存储器控制器。 每个这样的外设可以耦合到中断消息电路的一个实例。 在一个实施例中，中断是电平敏感的。 中断消息电路可以被配置为向中断控制器发送中断设置消息中断清除消息以指示电平。