公开(公告)号：US5568420A

公开(公告)日：1996-10-22

申请号：US350162

申请日：1994-11-30

Applicant: Young-Ho Lim ,  Kang-Deog Suh

Inventor： Young-Ho Lim ,  Kang-Deog Suh

IPC: G11C17/00 ,  G11C16/00 ,  G11C16/04 ,  G11C16/06 ,  G11C16/08 ,  G11C11/34

CPC classification number: G11C16/08 ,  G11C16/0483

Abstract: The present invention provides an electrically erasable and programmable nonvolatile semiconductor memory device (EEPROM) with NAND structured cells which is capable of reducing the number of peripheral circuits required to drive each memory block. The EEPROM according to the present invention includes memory blocks having transfer transistors controlled by a memory block selection signal, wherein the transfer transistors serve as a path through which control gate driving signals are supplied, and wherein control gate driving signals are applied to word lines at full voltage due to a self-boosting operation of each transfer transistor.

Abstract translation: 本发明提供了具有NAND结构单元的电可擦除和可编程的非易失性半导体存储器件（EEPROM），其能够减少驱动每个存储器块所需的外围电路的数量。 根据本发明的EEPROM包括具有由存储块选择信号控制的传输晶体管的存储块，其中传输晶体管用作提供控制栅极驱动信号的路径，并且其中控制栅极驱动信号被施加到字线 由于每个传输晶体管的自升压操作而导致全电压。

公开(公告)号：US08493785B2

公开(公告)日：2013-07-23

申请号：US13465246

申请日：2012-05-07

Applicant: Sung-Soo Lee ,  Young-Ho Lim ,  Hyun-Chul Cho ,  Dong-Hyuk Chae

Inventor： Sung-Soo Lee ,  Young-Ho Lim ,  Hyun-Chul Cho ,  Dong-Hyuk Chae

IPC: G11C11/34

CPC classification number: G11C16/0483 ,  G11C16/26

Abstract: A non-volatile memory device includes a memory cell array which includes a plurality of non-volatile memory cells, a plurality of word lines, and a plurality of bit lines. The memory device further includes an internal data output line for outputting data read from the bit lines of the memory array, and a page buffer operatively connected between a bit line of the memory cell array and the internal data output line. The page buffer includes a sense node which is selectively connected to the bit line, a latch circuit having a latch node which is selectively connected to the sense node, a latch input path which sets a logic voltage of the latch node in the programming mode and the read mode, and a latch output path which is separate from the latch input path.

Abstract translation: 非易失性存储器件包括存储单元阵列，其包括多个非易失性存储器单元，多个字线和多个位线。 存储器件还包括用于输出从存储器阵列的位线读取的数据的内部数据输出线以及可操作地连接在存储单元阵列的位线和内部数据输出线之间的页缓冲器。 页面缓冲器包括选择性地连接到位线的感测节点，具有选择性地连接到感测节点的锁存节点的锁存电路，将锁存节点的逻辑电压设置为编程模式的锁存器输入路径，以及 读取模式和与锁存器输入路径分离的锁存器输出路径。

公开(公告)号：US20130003455A1

公开(公告)日：2013-01-03

申请号：US13561204

申请日：2012-07-30

Applicant: Dong-Hyuk CHAE ,  Young-Ho LIM

Inventor： Dong-Hyuk CHAE ,  Young-Ho LIM

IPC: G11C16/10

CPC classification number: G06F12/0246 ,  G06F2212/7203

Abstract: A nonvolatile semiconductor memory device for an efficient program of multilevel data includes a memory cell array having a plurality of banks and a cache block corresponding to each of the plurality of banks. The cache block has a predetermined data storage capacity. A page buffer is included which corresponds to each of the plurality of banks. A programming circuit programs all of the plurality of banks except a last of said banks with page data. The page data is loaded through each page buffer and programmed into each cache block such that when page data for the last bank is loaded into the page buffer, the loaded page data and the page data programmed into the respective cache blocks are programmed into respective corresponding banks.

Abstract translation: 用于多电平数据的高效程序的非易失性半导体存储器件包括具有多个存储体的存储单元阵列和与多个存储体中的每一个对应的高速缓存块。 高速缓存块具有预定的数据存储容量。 包括对应于多个存储体中的每一个的页面缓冲器。 编程电路使用页面数据对除了最后的所述存储体之外的所有多个存储体进行编程。 页面数据通过每个页面缓冲器加载并被编程到每个缓存块中，使得当最后一个存储体的页面数据被加载到页面缓冲器中时，加载的页面数据和编入各个缓存块中的页面数据被编程到相应的对应的 银行。

公开(公告)号：US07768831B2

公开(公告)日：2010-08-03

申请号：US12109466

申请日：2008-04-25

Applicant: Dae-Seok Byeon ,  Young-Ho Lim

Inventor： Dae-Seok Byeon ,  Young-Ho Lim

IPC: G11C16/06

CPC classification number: G11C16/10 ,  G11C8/10 ,  G11C8/12 ,  G11C29/806 ,  G11C29/844

Abstract: A flash memory device includes multiple memory blocks, a decoder configured to select at least one of the memory blocks in response to block select signals, and a controller configured to generate the block select signals in response to a block address. When the block address corresponds to a bad block, the controller generates the block select signals to cause the decoder to interrupt selection of a memory block corresponding to the block address.

Abstract translation: 闪存器件包括多个存储器块，被配置为响应于块选择信号来选择至少一个存储器块的解码器，以及被配置为响应于块地址产生块选择信号的控制器。 当块地址对应于坏块时，控制器产生块选择信号以使解码器中断对应于块地址的存储块的选择。

公开(公告)号：US07692967B2

公开(公告)日：2010-04-06

申请号：US11776729

申请日：2007-07-12

Applicant: Dae-Seok Byeon ,  Young-ho Lim

Inventor： Dae-Seok Byeon ,  Young-ho Lim

IPC: G11C11/34

CPC classification number: G11C16/3418 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/30 ,  G11C16/3427

Abstract: A method of programming a nonvolatile memory device using hybrid local boosting which includes a plurality of cell strings each having a plurality of electrically erasable and programmable memory cells connected in series and a plurality of wordlines respectively connected to control gates of the plurality of memory cells. The address of a selected cell that is to be programmed is received. A determination is made as to whether a selected wordline connected to the selected cell is located above or under a reference wordline based on the received address. The selected cell is programmed using local boosting when the selected wordline corresponds to the reference wordline or is located above the reference wordline. The selected cell is programmed using self-boosting when the selected wordline is located under the reference wordline. The programming method reduces circuit size of a nonvolatile memory device employing the programming method and efficiently prevents program disturbance due to charge sharing.

Abstract translation: 一种使用混合局部升压来编程非易失性存储器件的方法，该方法包括多个单元串，每个单元串具有分别连接到多个存储器单元的控制栅极的多个电可擦除可编程存储器单元和多个字线。 接收要编程的所选单元的地址。 确定连接到所选择的单元的所选择的字线是否位于参考字线的上方或下方，基于所接收的地址。 当所选择的字线对应于参考字线或位于参考字线上方时，使用本地升压来编程所选单元格。 当所选择的字线位于参考字线下方时，使用自增强来对所选择的单元进行编程。 编程方法减少了使用编程方法的非易失性存储器件的电路尺寸，并且有效地防止了由于电荷共享引起的程序干扰。

公开(公告)号：US07561467B2

公开(公告)日：2009-07-14

申请号：US11657697

申请日：2007-01-25

Applicant: Dong-Ku Kang ,  Young-Ho Lim ,  Sang-Gu Kang

Inventor： Dong-Ku Kang ,  Young-Ho Lim ,  Sang-Gu Kang

IPC: G11C11/34

CPC classification number: G11C16/3454 ,  G11C11/5628 ,  G11C2211/5621 ,  G11C2211/5642 ,  G11C2211/5643

Abstract: A method is for programming a flash memory device which includes a plurality of memory cells storing multi-bit data representing one of a plurality of states. The method includes programming the multi-bit data into selected memory cells of the plurality of memory cells, the programming including a first verify-reading operation performed by a first verifying voltage, determining whether to execute a reprogramming operation for each of the selected memory cells, and reprogramming the selected memory cells in accordance with the determination. The reprogramming of the selected memory cells includes a second verify-reading operation performed by a second verifying voltage, the second verifying voltage being higher than the first verifying voltage.

Abstract translation: 一种用于对闪速存储器件进行编程的方法，该闪存器件包括存储表示多种状态之一的多位数据的多个存储器单元。 该方法包括将多位数据编程到多个存储单元的选定存储单元中，该程序包括由第一验证电压执行的第一验证读取操作，确定是否对所选存储单元中的每一个执行重编程操作 ，并且根据该确定重新编程所选择的存储单元。 所选择的存储单元的重新编程包括由第二验证电压执行的第二验证读取操作，第二验证电压高于第一验证电压。

公开(公告)号：US07525850B2

公开(公告)日：2009-04-28

申请号：US11941101

申请日：2007-11-16

Applicant: Dong Hyuk Chae ,  Young Ho Lim

Inventor： Dong Hyuk Chae ,  Young Ho Lim

IPC: G11C7/10

CPC classification number: G11C11/5642 ,  G11C16/0483 ,  G11C16/26 ,  G11C2211/5642

Abstract: A nonvolatile semiconductor memory device is provided which includes a memory array, a page buffer, and a row decoder. The memory array includes a plurality of nonvolatile memory cells, a bit line, and a word line, and the row decoder driven to control the word line of the memory array. The page buffer is electrically connected to the bit line and includes a main data latch and a sub-data latch. The page buffer, which is configured such that flipping of the main data latch is inhibited according to a logic state of the sub-data latch, further includes a main latch block, a sub-latch block, and a latch control block. The main latch block drives the main data latch and maps a logic state of the main data latch to a threshold voltage of a corresponding memory cell through the bit line. The sub-latch block drives the sub-data latch, where the sub-data latch is flipped depending on the voltage level of the bit line. The latch control block selectively flips the main data latch depending on the voltage level of the bit line, where the latch control block is disabled depending on a logic state of the sub-data latch.

Abstract translation: 提供一种包括存储器阵列，页缓冲器和行解码器的非易失性半导体存储器件。 存储器阵列包括多个非易失性存储器单元，位线和字线，并且行解码器被驱动以控制存储器阵列的字线。 页缓冲器电连接到位线，并包括主数据锁存器和子数据锁存器。 根据子数据锁存器的逻辑状态禁止主数据锁存器翻转的页缓冲器还包括主锁存块，子锁存块和锁存控制块。 主锁存块驱动主数据锁存器，并通过位线将主数据锁存器的逻辑状态映射到相应存储器单元的阈值电压。 子锁存块驱动子数据锁存器，其中子数据锁存器根据位线的电压电平翻转。 锁存控制块根据位线的电压电平有选择地翻转主数据锁存器，根据子数据锁存器的逻辑状态，锁存器控制块被禁用。

公开(公告)号：US20090052257A1

公开(公告)日：2009-02-26

申请号：US12172904

申请日：2008-07-14

Applicant: Jung-Hoon PARK ,  Sung-Soo LEE ,  Young-Ho LIM ,  Chang-Sub LEE ,  Ki-Tae PARK

Inventor： Jung-Hoon PARK ,  Sung-Soo LEE ,  Young-Ho LIM ,  Chang-Sub LEE ,  Ki-Tae PARK

IPC: G11C16/06 ,  G11C8/08

CPC classification number: G11C16/3418 ,  G11C16/0483 ,  G11C16/26 ,  G11C16/3427

Abstract: A method of reading a flash memory device can include driving a selected word line by applying a selection voltage thereto and driving unselected word lines by applying a first voltage thereto, driving the unselected word lines and first and second selection lines by applying a second voltage that is higher than the first voltage thereto, and reading data from a memory cell that is coupled to the selected word line.

Abstract translation: 一种读取闪速存储器件的方法可以包括通过向其施加选择电压来驱动所选择的字线并通过向其施加第一电压来驱动未选择的字线，通过施加第二电压来驱动未选择的字线和第一和第二选择线， 高于其第一电压，并且从耦合到所选字线的存储单元读取数据。

公开(公告)号：US07414890B2

公开(公告)日：2008-08-19

申请号：US11605227

申请日：2006-11-29

Applicant: Dae-Seok Byeon ,  Young-Ho Lim

Inventor： Dae-Seok Byeon ,  Young-Ho Lim

IPC: G11C16/04 ,  G11C5/14

CPC classification number: G11C16/30 ,  G11C5/145 ,  G11C8/10 ,  G11C16/0483 ,  G11C16/08 ,  H02M3/07

Abstract: A semiconductor memory device comprises a first pump clock generator configured to generate a first pump clock signal based on a first power supply voltage. The device also comprises a first charge pump configured to generate a first pump output voltage in response to the first pump clock signal. The device also comprises a second pump clock generator configured to generate a second pump clock signal based on the first pump output voltage. The device also comprises a second charge pump configured to generate a second pump output voltage in response to the second pump clock signal. The device also comprises a third pump clock generator configured to generate a third pump clock signal based on the first power supply voltage. The device also comprises a third charge pump configured to generate a third pump output voltage in response to the third pump clock signal.

Abstract translation: 半导体存储器件包括被配置为基于第一电源电压产生第一泵时钟信号的第一泵时钟发生器。 该装置还包括配置成响应于第一泵时钟信号产生第一泵输出电压的第一电荷泵。 该装置还包括被配置为基于第一泵输出电压产生第二泵时钟信号的第二泵时钟发生器。 该装置还包括配置成响应于第二泵时钟信号产生第二泵输出电压的第二电荷泵。 该装置还包括配置成基于第一电源电压产生第三泵时钟信号的第三泵时钟发生器。 该装置还包括配置成响应于第三泵时钟信号产生第三泵输出电压的第三电荷泵。

公开(公告)号：US07397706B2

公开(公告)日：2008-07-08

申请号：US11381556

申请日：2006-05-04

Applicant: Dae-Seok Byeon ,  Young-Ho Lim

Inventor： Dae-Seok Byeon ,  Young-Ho Lim

IPC: G11C16/04 ,  G11C16/06

CPC classification number: G11C16/16

Abstract: Methods of erasing data in a flash memory device are provided in which a plurality of wordline bias voltages are generated that include wordline bias voltages having at least two different levels, erasing data by applying the different wordline bias voltages to respective ones of a plurality of wordlines while applying an erasing voltage to a bulk region of memory cells, and verifying the erased states of the memory cells. Pursuant to these methods, the spread of the threshold-voltage distribution profile that may result from deviations of erasure-coupling ratios between memory cells may be reduced.

Abstract translation: 提供擦除闪速存储器件中的数据的方法，其中产生多个字线偏置电压，其包括具有至少两个不同电平的字线偏置电压，通过将不同的字线偏置电压施加到多个字线中的相应字线来擦除数据 同时将擦除电压施加到存储器单元的主体区域，以及验证存储器单元的擦除状态。 根据这些方法，可能会降低可能由存储器单元之间的擦除耦合比的偏差导致的阈值 - 电压分布曲线的扩展。