公开(公告)号：US07561467B2

公开(公告)日：2009-07-14

申请号：US11657697

申请日：2007-01-25

Applicant: Dong-Ku Kang ,  Young-Ho Lim ,  Sang-Gu Kang

Inventor： Dong-Ku Kang ,  Young-Ho Lim ,  Sang-Gu Kang

IPC: G11C11/34

CPC classification number: G11C16/3454 ,  G11C11/5628 ,  G11C2211/5621 ,  G11C2211/5642 ,  G11C2211/5643

Abstract: A method is for programming a flash memory device which includes a plurality of memory cells storing multi-bit data representing one of a plurality of states. The method includes programming the multi-bit data into selected memory cells of the plurality of memory cells, the programming including a first verify-reading operation performed by a first verifying voltage, determining whether to execute a reprogramming operation for each of the selected memory cells, and reprogramming the selected memory cells in accordance with the determination. The reprogramming of the selected memory cells includes a second verify-reading operation performed by a second verifying voltage, the second verifying voltage being higher than the first verifying voltage.

Abstract translation: 一种用于对闪速存储器件进行编程的方法，该闪存器件包括存储表示多种状态之一的多位数据的多个存储器单元。 该方法包括将多位数据编程到多个存储单元的选定存储单元中，该程序包括由第一验证电压执行的第一验证读取操作，确定是否对所选存储单元中的每一个执行重编程操作 ，并且根据该确定重新编程所选择的存储单元。 所选择的存储单元的重新编程包括由第二验证电压执行的第二验证读取操作，第二验证电压高于第一验证电压。

公开(公告)号：US20080056007A1

公开(公告)日：2008-03-06

申请号：US11657697

申请日：2007-01-25

Applicant: Dong-Ku Kang ,  Young-Ho Lim ,  Sang-Gu Kang

Inventor： Dong-Ku Kang ,  Young-Ho Lim ,  Sang-Gu Kang

IPC: G11C11/34

CPC classification number: G11C16/3454 ,  G11C11/5628 ,  G11C2211/5621 ,  G11C2211/5642 ,  G11C2211/5643

Abstract: A method is for programming a flash memory device which includes a plurality of memory cells storing multi-bit data representing one of a plurality of states. The method includes programming the multi-bit data into selected memory cells of the plurality of memory cells, the programming including a first verify-reading operation performed by a first verifying voltage, determining whether to execute a reprogramming operation for each of the selected memory cells, and reprogramming the selected memory cells in accordance with the determination. The reprogramming of the selected memory cells includes a second verify-reading operation performed by a second verifying voltage, the second verifying voltage being higher than the first verifying voltage.

Abstract translation: 一种用于对闪速存储器件进行编程的方法，该闪存器件包括存储表示多种状态之一的多位数据的多个存储器单元。 该方法包括将多位数据编程到多个存储单元的选定存储单元中，该程序包括由第一验证电压执行的第一验证读取操作，确定是否对所选存储单元中的每一个执行重编程操作 ，并且根据该确定重新编程所选择的存储单元。 所选择的存储单元的重新编程包括由第二验证电压执行的第二验证读取操作，第二验证电压高于第一验证电压。

公开(公告)号：US07505313B2

公开(公告)日：2009-03-17

申请号：US11593478

申请日：2006-11-07

Applicant: Dong-Ku Kang ,  Young-Ho Lim

Inventor： Dong-Ku Kang ,  Young-Ho Lim

IPC: G11C11/34

CPC classification number: G11C11/5628 ,  G11C16/0483 ,  G11C2211/5621

Abstract: A program method of a flash memory device having first and-second bitlines connected with a plurality of memory cells for storing multi-bit data indicating one of a plurality of states. The program method includes programming memory cells, connected to a selected row and first or second bitlines, with multi-bit data; and reprogramming programmed memory cells connected to a row disposed directly below the selected row and the first bitlines or the second bitlines, whereby increasing a read margin between adjacent states reduced due to high temperature stress (HTS).

Abstract translation: 一种闪速存储装置的编程方法，具有与多个存储单元连接的第一和第二位线，用于存储指示多个状态之一的多位数据。 程序方法包括利用多位数据编程连接到所选行和第一或第二位线的存储器单元; 并且重新编程连接到直接位于所选择的行下方的行和第一位线或第二位线的编程存储器单元，由此增加由于高温应力（HTS）引起的相邻状态之间的读取余量减小。

公开(公告)号：US20070159892A1

公开(公告)日：2007-07-12

申请号：US11513159

申请日：2006-08-31

Applicant: Dong-Ku Kang ,  Young-Ho Lim

Inventor： Dong-Ku Kang ,  Young-Ho Lim

IPC: G11C16/04

CPC classification number: G11C16/12 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/3418 ,  G11C2211/5621

Abstract: A programming method of a flash memory device having a plurality of memory cells for storing multi-bit data indicating one of a plurality of states. The programming method includes programming selected memory cells using multi-bit data to have one of the states; detecting programmed memory cells arranged within a predetermined region of threshold voltage distribution each corresponding to at least two of the states, wherein predetermined regions of the respective at least two states are selected by one of a first verify voltage and a read voltage and a second verify voltage, the first verify voltage being lower than the second verify voltage and higher than the read voltage; and simultaneously programming detected memory cells of the at least two states to have a threshold voltage being equivalent to or higher than the second verify voltage corresponding to each of the states.

Abstract translation: 一种具有多个存储单元的闪速存储器件的编程方法，用于存储指示多个状态之一的多位数据。 编程方法包括使用多位数据对所选择的存储单元进行编程以具有其中一种状态; 检测布置在每个对应于至少两个状态的阈值电压分布的预定区域内的程序存储器单元，其中相应的至少两个状态的预定区域由第一验证电压和读取电压中的一个选择，并且第二验证 电压，第一验证电压低于第二验证电压并高于读取电压; 同时对所述至少两个状态的检测到的存储单元进行编程，以使阈值电压等于或高于对应于每个状态的第二验证电压。

公开(公告)号：US20070159889A1

公开(公告)日：2007-07-12

申请号：US11522406

申请日：2006-09-18

Applicant: Dong-Ku Kang ,  Young-Ho Lim

Inventor： Dong-Ku Kang ,  Young-Ho Lim

IPC: G11C16/04 ,  G11C11/34 ,  G11C16/06

CPC classification number: G11C16/0483 ,  G11C11/5628 ,  G11C16/12 ,  G11C16/3454 ,  G11C16/3459 ,  G11C2211/5621

Abstract: A program method of a flash memory device including a plurality of memory cells for storing multi-bit data indicating one of states. The program method includes programming memory cells selected to have one of the states by using multi-bit data; detecting programmed memory cells within a predetermined region of a threshold voltage distribution where the programmed memory cells having the respective states are distributed, wherein the predetermined region of the respective states is selected by one of a first verify voltage and a read voltage and a second voltage, the first verify voltage being lower than the second verify voltage and higher than the read voltage; and programming the detected memory cells to have a threshold voltage being equivalent to or higher than the second verify voltage corresponding to each of the states.

Abstract translation: 一种闪存器件的编程方法，包括用于存储指示状态之一的多位数据的多个存储器单元。 程序方法包括通过使用多位数据来编程选择为具有状态之一的存储器单元; 在阈值电压分布的预定区域内检测已编程的存储单元，其中具有各自状态的编程存储单元被分配，其中各个状态的预定区域由第一验证电压和读取电压和第二电压 第一验证电压低于第二验证电压并高于读取电压; 以及对检测到的存储单元进行编程，使阈值电压等于或高于对应于每个状态的第二验证电压。

公开(公告)号：US07468907B2

公开(公告)日：2008-12-23

申请号：US11522406

申请日：2006-09-18

Applicant: Dong-Ku Kang ,  Young-Ho Lim

Inventor： Dong-Ku Kang ,  Young-Ho Lim

IPC: G11C16/04

CPC classification number: G11C16/0483 ,  G11C11/5628 ,  G11C16/12 ,  G11C16/3454 ,  G11C16/3459 ,  G11C2211/5621

Abstract: A program method of a flash memory device including a plurality of memory cells for storing multi-bit data indicating one of states. The program method includes programming memory cells selected to have one of the states by using multi-bit data; detecting programmed memory cells within a predetermined region of a threshold voltage distribution where the programmed memory cells having the respective states are distributed, wherein the predetermined region of the respective states is selected by one of a first verify voltage and a read voltage and a second voltage, the first verify voltage being lower than the second verify voltage and higher than the read voltage; and programming the detected memory cells to have a threshold voltage being equivalent to or higher than the second verify voltage corresponding to each of the states.

Abstract translation: 一种闪存器件的编程方法，包括用于存储指示状态之一的多位数据的多个存储器单元。 程序方法包括通过使用多位数据来编程选择为具有状态之一的存储器单元; 在阈值电压分布的预定区域内检测已编程的存储单元，其中具有各自状态的编程存储单元被分配，其中各个状态的预定区域由第一验证电压和读取电压和第二电压 第一验证电压低于第二验证电压并高于读取电压; 以及对检测到的存储单元进行编程，使阈值电压等于或高于对应于每个状态的第二验证电压。

公开(公告)号：US07463526B2

公开(公告)日：2008-12-09

申请号：US11513159

申请日：2006-08-31

Applicant: Dong-Ku Kang ,  Young-Ho Lim

Inventor： Dong-Ku Kang ,  Young-Ho Lim

IPC: G11C11/34

CPC classification number: G11C16/12 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/3418 ,  G11C2211/5621

Abstract: A programming method of a flash memory device having a plurality of memory cells for storing multi-bit data indicating one of a plurality of states. The programming method includes programming selected memory cells using multi-bit data to have one of the states; detecting programmed memory cells arranged within a predetermined region of threshold voltage distribution each corresponding to at least two of the states, wherein predetermined regions of the respective at least two states are selected by one of a first verify voltage and a read voltage and a second verify voltage, the first verify voltage being lower than the second verify voltage and higher than the read voltage; and simultaneously programming detected memory cells of the at least two states to have a threshold voltage being equivalent to or higher than the second verify voltage corresponding to each of the states.

Abstract translation: 一种具有多个存储单元的闪速存储器件的编程方法，用于存储指示多个状态之一的多位数据。 编程方法包括使用多位数据对所选择的存储单元进行编程以具有其中一种状态; 检测布置在每个对应于至少两个状态的阈值电压分布的预定区域内的程序存储器单元，其中相应的至少两个状态的预定区域由第一验证电压和读取电压中的一个选择，并且第二验证 电压，第一验证电压低于第二验证电压并高于读取电压; 同时对所述至少两个状态的检测到的存储单元进行编程，以使阈值电压等于或高于对应于每个状态的第二验证电压。

公开(公告)号：US20070171726A1

公开(公告)日：2007-07-26

申请号：US11593478

申请日：2006-11-07

Applicant: Dong-Ku Kang ,  Young-Ho Lim

Inventor： Dong-Ku Kang ,  Young-Ho Lim

IPC: G11C16/04 ,  G11C16/06 ,  G11C11/34 ,  G11C8/00

CPC classification number: G11C11/5628 ,  G11C16/0483 ,  G11C2211/5621

Abstract: A program method of a flash memory device having first and-second bitlines connected with a plurality of memory cells for storing multi-bit data indicating one of a plurality of states. The program method includes programming memory cells, connected to a selected row and first or second bitlines, with multi-bit data; and reprogramming programmed memory cells connected to a row disposed directly below the selected row and the first bitlines or the second bitlines, whereby increasing a read margin between adjacent states reduced due to high temperature stress (HTS).

Abstract translation: 一种闪速存储装置的编程方法，具有与多个存储单元连接的第一和第二位线，用于存储指示多个状态之一的多位数据。 程序方法包括利用多位数据编程连接到所选行和第一或第二位线的存储器单元; 并且重新编程连接到直接位于所选择的行下方的行和第一位线或第二位线的编程存储器单元，由此增加由于高温应力（HTS）引起的相邻状态之间的读取余量减小。

公开(公告)号：US08477533B2

公开(公告)日：2013-07-02

申请号：US13402922

申请日：2012-02-23

Applicant: Dong-Ku Kang

Inventor： Dong-Ku Kang

IPC: G11C16/04

CPC classification number: G11C16/26 ,  G11C11/5642

Abstract: A flash memory device and a reading method are provided where memory cells are divided into at least two groups. Memory cells are selected according to a threshold voltage distribution. Data stored in the selected memory cells are detected and the data is latched corresponding to one of the at least two groups according to a first read operation. A second read operation detects and latches data of the memory cells corresponding to another one of the at least two groups. The data is processed through a soft decision algorithm during the second read operation.

公开(公告)号：US07791938B2

公开(公告)日：2010-09-07

申请号：US12169109

申请日：2008-07-08

Applicant: Dong-Ku Kang ,  Seung-Jae Lee ,  Jun-Jin Kong

Inventor： Dong-Ku Kang ,  Seung-Jae Lee ,  Jun-Jin Kong

IPC: G11C11/34 ,  G11C16/04

CPC classification number: G11C11/5642 ,  G06F11/1068 ,  G11C16/0483 ,  G11C16/26 ,  G11C16/3418 ,  G11C2029/0411

Abstract: A flash memory system includes a multi-bit flash memory device having a memory cell array including memory cells arranged in rows and columns; a read circuit configured to read data from the memory cell array; and control logic configured to control the read circuit so as to successively read data from a selected memory cell and adjacent memory cells to the selected memory cell in response to a request for a read operation with respect to MSB data stored in the selected memory cell. A compare circuit is configured to compare data read from the adjacent memory cells to the selected memory cell provided from the multi-bit flash memory device and to correct data read from the selected memory cells based upon the comparison result.

Abstract translation: 闪存系统包括具有存储单元阵列的多位闪存器件，该存储器单元阵列包括以行和列排列的存储器单元; 读取电路，被配置为从存储单元阵列读取数据; 以及控制逻辑，被配置为控制所述读取电路，以便响应于对存储在所选择的存储器单元中的MSB数据的读取操作的请求，连续地将数据从所选择的存储器单元和相邻存储器单元读取到所选择的存储器单元。 比较电路被配置为将从相邻存储器单元读取的数据与从多位闪存器件提供的所选择的存储器单元进行比较，并且基于比较结果校正从所选存储器单元读取的数据。