公开(公告)号：US20120079173A1

公开(公告)日：2012-03-29

申请号：US13239494

申请日：2011-09-22

Applicant: Dong-Hyuk CHAE ,  Young-Ho LIM

Inventor： Dong-Hyuk CHAE ,  Young-Ho LIM

IPC: G06F12/00

CPC classification number: G06F12/0246 ,  G06F2212/7203

Abstract: A nonvolatile semiconductor memory device includes a memory cell array having a plurality of banks and a cache block corresponding to each of the plurality of banks. The cache block has a predetermined data storage capacity. A page buffer is included which corresponds to each of the plurality of banks. A programming circuit programs all of the plurality of banks except a last of said banks with page data. The page data is loaded through each page buffer and programmed into each cache block such that when page data for the last bank is loaded into the page buffer, the loaded page data and the page data programmed into the respective cache blocks are programmed into respective corresponding banks.

Abstract translation: 非易失性半导体存储器件包括具有多个存储体的存储单元阵列和与多个存储体中的每一个对应的高速缓存块。 高速缓存块具有预定的数据存储容量。 包括对应于多个存储体中的每一个的页面缓冲器。 编程电路使用页面数据对除了最后的所述存储体之外的所有多个存储体进行编程。 页面数据通过每个页面缓冲器加载并被编程到每个缓存块中，使得当最后一个存储体的页面数据被加载到页面缓冲器中时，加载的页面数据和编入各个缓存块中的页面数据被编程到相应的对应的 银行。

公开(公告)号：US08085589B2

公开(公告)日：2011-12-27

申请号：US12881321

申请日：2010-09-14

Applicant: Moo-Sung Kim ,  Young-Ho Lim

Inventor： Moo-Sung Kim ,  Young-Ho Lim

IPC: G11C16/04

CPC classification number: G11C16/3418 ,  G11C16/10 ,  G11C16/3427

Abstract: A method of programming a flash memory includes programming memory cells connected to a selected word line by applying a first voltage to the selected word line and a second voltage to non-selected word lines, the second voltage being lower than the first voltage, lowering the first voltage of the selected word line to a third voltage after programming the memory cells connected to the selected word line, the third voltage being lower than the first voltage, and recovering a fourth voltage of the selected word line and the non-selected word lines, the fourth voltage being lower than the second and third voltages.

Abstract translation: 一种对闪存进行编程的方法包括通过向所选择的字线施加第一电压并将第二电压施加到未选择的字线来连接到所选字线的编程存储单元，所述第二电压低于所述第一电压， 在对连接到所选字线的存储单元进行编程之后，所选字线的第一电压为第三电压，第三电压低于第一电压，并且恢复所选字线和未选字线的第四电压 ，第四电压低于第二和第三电压。

公开(公告)号：US08045380B2

公开(公告)日：2011-10-25

申请号：US12939251

申请日：2010-11-04

Applicant: Dae-Seok Byeon ,  Young-Ho Lim

Inventor： Dae-Seok Byeon ,  Young-Ho Lim

IPC: G11C16/04

CPC classification number: G11C16/0483 ,  G11C16/10

Abstract: A flash memory and a program method of the flash memory include applying a pass voltage to word lines to boost a channel voltage, which is discharged to a ground voltage. A program voltage is applied to a selected word line and a local voltage is applied to at least one word line supplied with the pass voltage while the program voltage is being applied to the selected word line. The local voltage is lower than the pass voltage and equal to or higher than the ground voltage. The boosted channel voltage may be discharged before the program voltage is applied to the selected word line.

Abstract translation: 闪速存储器和闪速存储器的编程方法包括对字线施加通过电压以升高被释放到接地电压的通道电压。 一个编程电压被施加到所选择的字线，并且当编程电压被施加到所选择的字线时，局部电压被施加到提供有通过电压的至少一个字线。 局部电压低于通过电压，等于或高于接地电压。 在将编程电压施加到所选择的字线之前，升压的通道电压可以被放电。

公开(公告)号：US07974125B2

公开(公告)日：2011-07-05

申请号：US12822246

申请日：2010-06-24

Applicant: Dae-Seok Byeon ,  Young-Ho Lim

Inventor： Dae-Seok Byeon ,  Young-Ho Lim

IPC: G11C16/06

CPC classification number: G11C16/10 ,  G11C8/10 ,  G11C8/12 ,  G11C29/806 ,  G11C29/844

Abstract: A flash memory device includes multiple memory blocks, a decoder configured to select at least one of the memory blocks in response to block select signals, a controller configured to generate the block select signals in response to a block address and to generate a flag signal when the block address corresponds to a bad block, and an output buffer configured to output fixed data in response to the flag signal indicating that the block address corresponds to the bad block. When the block address corresponds to a bad block, the controller generates the block select signals to cause the decoder to interrupt selection of a memory block corresponding to the block address.

Abstract translation: 闪速存储器件包括多个存储器块，被配置为响应于块选择信号来选择至少一个存储器块的解码器，被配置为响应于块地址产生块选择信号并且产生标志信号的控制器， 块地址对应于坏块，并且输出缓冲器被配置为响应于指示块地址对应于坏块的标志信号输出固定数据。 当块地址对应于坏块时，控制器产生块选择信号以使解码器中断对应于块地址的存储块的选择。

公开(公告)号：US07965558B2

公开(公告)日：2011-06-21

申请号：US12721913

申请日：2010-03-11

Applicant: Dong-Hyuk Chae ,  Young-Ho Lim

Inventor： Dong-Hyuk Chae ,  Young-Ho Lim

IPC: G11C11/34

CPC classification number: G11C16/12 ,  G11C5/145 ,  G11C16/0483

Abstract: Methods of generating a program voltage for programming a non-volatile memory device include generating an initial voltage and generating a first ramping voltage in response to the initial voltage. The first ramping voltage has a ramping speed slower than the ramping speed of the initial voltage. A second ramping voltage is generated in response to the first ramping voltage. The second ramping voltage has a lower ripple than the first ramping voltage. The second ramping voltage is output as a program voltage for programming a non-volatile memory device. A program voltage generating circuit includes a program voltage generating unit configured to generate an initial voltage, a ramping circuit configured to generate a first ramping voltage responsive to the initial voltage, and a voltage controlling unit configured to generate a second ramping voltage having relatively low ripple and to output the first ramping voltage or the second ramping voltage responsive to a voltage level of the first ramping voltage. Semiconductor memory devices including program voltage generating circuits are also disclosed.

Abstract translation: 产生用于编程非易失性存储器件的编程电压的方法包括产生初始电压并响应于初始电压产生第一斜变电压。 第一斜坡电压的斜坡速度比初始电压的斜坡速度慢。 响应于第一斜坡电压产生第二斜坡电压。 第二斜坡电压具有比第一斜坡电压更低的纹波。 输出第二斜坡电压作为编程非易失性存储器件的编程电压。 一个编程电压发生电路包括：一个编程电压产生单元，被配置为产生一个初始电压;一个斜坡电路，被配置为产生一个响应初始电压的第一斜坡电压;以及一个电压控制单元，被配置为产生一个具有相对低纹波的第二斜坡电压 并且响应于第一斜坡电压的电压电平而输出第一斜坡电压或第二斜坡电压。 还公开了包括程序电压产生电路的半导体存储器件。

公开(公告)号：US07787306B2

公开(公告)日：2010-08-31

申请号：US12172904

申请日：2008-07-14

Applicant: Jung-Hoon Park ,  Sung-Soo Lee ,  Young-Ho Lim ,  Chang-Sub Lee ,  Ki-Tae Park

Inventor： Jung-Hoon Park ,  Sung-Soo Lee ,  Young-Ho Lim ,  Chang-Sub Lee ,  Ki-Tae Park

IPC: G11C16/06

CPC classification number: G11C16/3418 ,  G11C16/0483 ,  G11C16/26 ,  G11C16/3427

Abstract: A method of reading a flash memory device can include driving a selected word line by applying a selection voltage thereto and driving unselected word lines by applying a first voltage thereto, driving the unselected word lines and first and second selection lines by applying a second voltage that is higher than the first voltage thereto, and reading data from a memory cell that is coupled to the selected word line.

Abstract translation: 一种读取闪速存储器件的方法可以包括通过向其施加选择电压来驱动所选择的字线并通过向其施加第一电压来驱动未选择的字线，通过施加第二电压来驱动未选择的字线和第一和第二选择线， 高于其第一电压，并且从耦合到所选字线的存储单元读取数据。

公开(公告)号：US20100165742A1

公开(公告)日：2010-07-01

申请号：US12721913

申请日：2010-03-11

Applicant: Dong-Hyuk Chae ,  Young-Ho Lim

Inventor： Dong-Hyuk Chae ,  Young-Ho Lim

IPC: G11C16/04 ,  G05F1/10

CPC classification number: G11C16/12 ,  G11C5/145 ,  G11C16/0483

Abstract: Methods of generating a program voltage for programming a non-volatile memory device include generating an initial voltage and generating a first ramping voltage in response to the initial voltage. The first ramping voltage has a ramping speed slower than the ramping speed of the initial voltage. A second ramping voltage is generated in response to the first ramping voltage. The second ramping voltage has a lower ripple than the first ramping voltage. The second ramping voltage is output as a program voltage for programming a non-volatile memory device. A program voltage generating circuit includes a program voltage generating unit configured to generate an initial voltage, a ramping circuit configured to generate a first ramping voltage responsive to the initial voltage, and a voltage controlling unit configured to generate a second ramping voltage having relatively low ripple and to output the first ramping voltage or the second ramping voltage responsive to a voltage level of the first ramping voltage. Semiconductor memory devices including program voltage generating circuits are also disclosed.

Abstract translation: 产生用于编程非易失性存储器件的编程电压的方法包括产生初始电压并响应于初始电压产生第一斜变电压。 第一斜坡电压的斜坡速度比初始电压的斜坡速度慢。 响应于第一斜坡电压产生第二斜坡电压。 第二斜坡电压具有比第一斜坡电压更低的纹波。 输出第二斜坡电压作为编程非易失性存储器件的编程电压。 一个编程电压发生电路包括：一个编程电压产生单元，被配置为产生一个初始电压;一个斜坡电路，被配置为产生一个响应初始电压的第一斜坡电压;以及一个电压控制单元，被配置为产生一个具有相对低纹波的第二斜坡电压 并且响应于第一斜坡电压的电压电平而输出第一斜坡电压或第二斜坡电压。 还公开了包括程序电压产生电路的半导体存储器件。

公开(公告)号：US07701772B2

公开(公告)日：2010-04-20

申请号：US12186087

申请日：2008-08-05

Applicant: Dong-Hyuk Chae ,  Young-Ho Lim

Inventor： Dong-Hyuk Chae ,  Young-Ho Lim

IPC: G11C16/04

CPC classification number: G11C16/12 ,  G11C5/145 ,  G11C16/0483

Abstract: Methods of generating a program voltage for programming a non-volatile memory device include generating an initial voltage and generating a first ramping voltage in response to the initial voltage. The first ramping voltage has a ramping speed slower than the ramping speed of the initial voltage. A second ramping voltage is generated in response to the first ramping voltage. The second ramping voltage has a lower ripple than the first ramping voltage. The second ramping voltage is output as a program voltage for programming a non-volatile memory device. A program voltage generating circuit includes a program voltage generating unit configured to generate an initial voltage, a ramping circuit configured to generate a first ramping voltage responsive to the initial voltage, and a voltage controlling unit configured to generate a second ramping voltage having relatively low ripple and to output the first ramping voltage or the second ramping voltage responsive to a voltage level of the first ramping voltage. Semiconductor memory devices including program voltage generating circuits are also disclosed.

Abstract translation: 产生用于编程非易失性存储器件的编程电压的方法包括产生初始电压并响应于初始电压产生第一斜变电压。 第一斜坡电压的斜坡速度比初始电压的斜坡速度慢。 响应于第一斜坡电压产生第二斜坡电压。 第二斜坡电压具有比第一斜坡电压更低的纹波。 输出第二斜坡电压作为编程非易失性存储器件的编程电压。 一个编程电压发生电路包括：一个编程电压产生单元，被配置为产生一个初始电压;一个斜坡电路，被配置为产生一个响应初始电压的第一斜坡电压;以及一个电压控制单元，被配置为产生一个具有相对低纹波的第二斜坡电压 并且响应于第一斜坡电压的电压电平而输出第一斜坡电压或第二斜坡电压。 还公开了包括程序电压产生电路的半导体存储器件。

公开(公告)号：US07697327B2

公开(公告)日：2010-04-13

申请号：US12145531

申请日：2008-06-25

Applicant: Moo-Sung Kim ,  Young-Ho Lim

Inventor： Moo-Sung Kim ,  Young-Ho Lim

IPC: G11C16/00

CPC classification number: G11C16/12 ,  G11C8/08 ,  G11C16/0483

Abstract: A NAND flash memory device and a programming method thereof capable of improving a program speed during a multi-level cell programming operation are provided. The device performs a programming operation using an ISPP method. Additionally, the device includes a memory cell storing multi-bit data; a program voltage generating circuit generating a program voltage to be supplied to the memory cell; and a program voltage controller controlling a start level of the program voltage. The device supplies an LSB start voltage to a selected word line during an LSB program, and an MSB start voltage higher than the LSB start voltage to the selected word line during an MSB program.

Abstract translation: 提供一种能够在多级单元编程操作期间提高编程速度的NAND快闪存储器件及其编程方法。 该设备使用ISPP方法执行编程操作。 另外，该设备包括存储多位数据的存储单元; 编程电压产生电路，产生要提供给存储单元的编程电压; 以及控制编程电压的起始电平的编程电压控制器。 在MSB程序期间，器件在LSB程序期间将LSB起始电压提供给所选择的字线，并在MSB程序期间向所选字线提供高于LSB起始电压的MSB启动电压。

公开(公告)号：US07675774B2

公开(公告)日：2010-03-09

申请号：US12333344

申请日：2008-12-12

Applicant: Sung-Soo Lee ,  Young-Ho Lim ,  Hyun-Chul Cho ,  Dong-Hyuk Chae

Inventor： Sung-Soo Lee ,  Young-Ho Lim ,  Hyun-Chul Cho ,  Dong-Hyuk Chae

IPC: G11C16/04

CPC classification number: G11C16/10 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/0483 ,  G11C2211/5642

Abstract: According to one aspect, a memory cell array includes a bit line connected to a plurality of nonvolatile memory cells, where the nonvolatile memory cells are selectively programmable in any one of at least first, second, third and fourth threshold voltage states, and where the first, second, third and fourth threshold voltage states correspond to four different data values defined by first and second bits. A page buffer circuit stores a logic value as main latch data and is responsive to a main latch signal to selectively flip the logic value of the main latch data according to a voltage level of the bit line. A sub-latch circuit stores a logic value as sub-latch data and is responsive to a sub-latch signal to selectively flip the logic value of the sub-latch data according to the voltage level of the bit line. The memory device is operable in a read mode which reads the threshold voltage state of the non-volatile memory cells and a programming mode which programs the threshold voltage state of the non-volatile memory cells, wherein the page buffer circuit is selectively responsive to the sub-latch data to inhibit flipping of the logic value of the main latch data in the programming mode.

Abstract translation: 根据一个方面，存储单元阵列包括连接到多个非易失性存储单元的位线，其中非易失性存储单元可选择性地以至少第一，第二，第三和第四阈值电压状态中的任何一个编程，并且其中 第一，第二，第三和第四阈值电压状态对应于由第一和第二位定义的四个不同的数据值。 页面缓冲电路将逻辑值存储为主锁存数据，并且响应于主锁存信号，以根据位线的电压电平选择性地翻转主锁存数据的逻辑值。 子锁存电路将逻辑值存储为子锁存数据，并且响应于子锁存信号，以根据位线的电压电平选择性地翻转子锁存数据的逻辑值。 存储器件可读取读取非易失性存储器单元的阈值电压状态的读取模式和编程非易失性存储器单元的阈值电压状态的编程模式，其中页面缓冲器电路有选择地响应于 子锁存数据，以禁止在编程模式下翻转主锁存器数据的逻辑值。