公开(公告)号：US07286401B2

公开(公告)日：2007-10-23

申请号：US11002794

申请日：2004-12-03

Applicant: Tetsuya Ishimaru ,  Takanori Yamazoe

Inventor： Tetsuya Ishimaru ,  Takanori Yamazoe

IPC: G11C16/04 ,  G11C14/00 ,  G11C7/00 ,  G11C8/00

CPC classification number: G11C16/0425 ,  G11C16/3418 ,  G11C16/3431 ,  G11C16/349

Abstract: Disclosed here is a nonvolatile semiconductor memory device used to prevent data loss that might occur in unselected memory cells due to a disturbance that might occur during programming/erasing in/from those memory cells. In the nonvolatile semiconductor memory device, the number of programming/erasing operations performed in a data storage block over a programming/erasing unit of the subject nonvolatile memory is recorded in an erasing/programming counter EW CT provided in each data storage block. When the value of the erasing/programming counter reaches a predetermined value, the data storage block corresponding to the erasing/programming counter is refreshed. In the refreshing operation, the data in the data storage block is stored in a temporary storing region provided in the data storage block, then the data in a temporary storing region of the data storage area is erased and the data stored temporarily is programmed in the data storage block again.

Abstract translation: 这里公开了一种非易失性半导体存储器件，用于防止由于在来自/来自这些存储器单元的编程/擦除期间可能发生的干扰而在未选择的存储单元中可能发生的数据丢失。 在非易失性半导体存储装置中，通过在非易失性存储器的编程/擦除单元上的数据存储块执行的编程/擦除操作的数量被记录在每个数据存储块中提供的擦除/编程计数器EW CT中。 当擦除/编程计数器的值达到预定值时，与擦除/编程计数器相对应的数据存储块被刷新。 在刷新操作中，数据存储块中的数据被存储在设置在数据存储块中的临时存储区域中，然后数据存储区域的临时存储区域中的数据被擦除，临时存储的数据被编程在 数据存储块。

公开(公告)号：US07212444B2

公开(公告)日：2007-05-01

申请号：US11137518

申请日：2005-05-26

Applicant: Digh Hisamoto ,  Kan Yasui ,  Tetsuya Ishimaru ,  Shinichiro Kimura ,  Daisuke Okada

Inventor： Digh Hisamoto ,  Kan Yasui ,  Tetsuya Ishimaru ,  Shinichiro Kimura ,  Daisuke Okada

IPC: G11C16/04 ,  G11C16/06

CPC classification number: G11C16/0425 ,  G11C16/12 ,  G11C16/14 ,  G11C16/26 ,  G11C16/3454 ,  G11C16/3459

Abstract: An operation scheme for operating stably a semiconductor nonvolatile memory device is provided.When hot-hole injection is conducted in the semiconductor nonvolatile memory device of a split gate structure, the hot-hole injection is verified using a crossing point that does not change with time. Thus, an erased state can be verified without being aware of any time-varying changes.Also, programming or programming/erasure is conducted by repeating pulse voltage or multi-step voltage application to a gate section multiple times.

公开(公告)号：US20070035155A1

公开(公告)日：2007-02-15

申请号：US10556566

申请日：2005-03-02

Applicant: Tetsuya Ishimaru ,  Ryu Kudo ,  Makoto Fujiwara

Inventor： Tetsuya Ishimaru ,  Ryu Kudo ,  Makoto Fujiwara

IPC: B62D25/06

CPC classification number: E02F9/00 ,  B60Y2200/41 ,  E02F9/0891 ,  E05B17/0037 ,  E05B63/04 ,  E05B77/00 ,  E05D3/145 ,  E05Y2900/518 ,  E05Y2900/536

Abstract: An opening and closing device for opening and closing a bonnet provided in the rear part of the machine body is arranged in such a manner as to ensure as large an opening portion to be formed when the bonnet is opened as possible. The opening and closing devices 18 and 19 for the bonnet 13 provided in the rear part of the machine body are adapted to have a 4-point supported link structure comprising: a bonnet side support plate 21 fixed integrally to the bonnet 13 and having first and second support members 21c and 21d provided, respectively, in the front and rear end portions thereof; a machine body side support plate 20 fixed integrally to a bracket for opening and closing device 17a that is provided in the rear frame 10 and having first and second support members 20c and 20d provided, respectively, in the front and rear end portions thereof; and first and second links 22 and 23 for movably connecting, respectively, the first support members 20c and 21c and the second support members 20d and 21d on the respective support plates 20 and 21.

Abstract translation: 用于打开和关闭设置在机体后部的发动机罩的打开和关闭装置被布置成确保当发动机罩尽可能打开时要形成的开口部分大。 用于设置在机体后部的发动机盖13的开闭装置18和19适于具有4点支撑的连杆结构，该连接结构包括：一体地固定在发动机罩13上的发动机罩侧支撑板21， 第二支撑构件21c和21d分别设置在其前端部和后端部分中; 整体地固定在用于打开和关闭装置17a的支架上的机体侧支撑板20，其设置在后框架10中，并且具有分别设置在前后端部中的第一和第二支撑构件20c和20d 的; 以及用于分别将第一支撑构件20c和21c以及第二支撑构件20d和21d可移动地连接在各个支撑板20和21上的第一和第二连杆22和23。

公开(公告)号：US20050265080A1

公开(公告)日：2005-12-01

申请号：US11137518

申请日：2005-05-26

Applicant: Digh Hisamoto ,  Kan Yasui ,  Tetsuya Ishimaru ,  Shinichiro Kimura ,  Daisuke Okada

Inventor： Digh Hisamoto ,  Kan Yasui ,  Tetsuya Ishimaru ,  Shinichiro Kimura ,  Daisuke Okada

IPC: G11C11/34 ,  G11C16/04 ,  G11C16/12 ,  G11C16/14 ,  G11C16/26 ,  G11C16/34

CPC classification number: G11C16/0425 ,  G11C16/12 ,  G11C16/14 ,  G11C16/26 ,  G11C16/3454 ,  G11C16/3459

Abstract: An operation scheme for operating stably a semiconductor nonvolatile memory device is provided. When hot-hole injection is conducted in the semiconductor nonvolatile memory device of a split gate structure, the hot-hole injection is verified using a crossing point that does not change with time. Thus, an erased state can be verified without being aware of any time-varying changes. Also, programming or programming/erasure is conducted by repeating pulse voltage or multi-step voltage application to a gate section multiple times.

Abstract translation: 提供一种稳定运行半导体非易失性存储器件的操作方案。 当在分裂栅极结构的半导体非易失性存储器件中进行热空穴注入时，使用不随时间变化的交叉点来验证热孔注入。 因此，可以验证擦除状态，而不知道任何时变变化。 此外，通过将多次脉冲电压或多级电压施加到栅极部分进行编程或编程/擦除。

公开(公告)号：US20110235419A1

公开(公告)日：2011-09-29

申请号：US13073988

申请日：2011-03-28

Applicant: Tetsuya ISHIMARU ,  Yasuhiro Shimamoto ,  Hideo Kasai ,  Yutaka Okuyama ,  Tsuyoshi Arigane

Inventor： Tetsuya ISHIMARU ,  Yasuhiro Shimamoto ,  Hideo Kasai ,  Yutaka Okuyama ,  Tsuyoshi Arigane

IPC: G11C16/04

CPC classification number: G11C16/10 ,  G11C16/0466 ,  G11C16/14 ,  G11C16/30 ,  H01L27/11563 ,  H01L29/42344

Abstract: In a split gate MONOS memory which carries out rewrite by hot carrier injection, retention characteristics are improved. A select gate electrode of a memory cell is connected to a select gate line, and a memory gate electrode is connected to a memory gate line. A drain region is connected to a bit line, and a source region is connected to a source line. Furthermore, a well line is connected to a p type well region in which the memory cell is formed. When write to the memory cell is to be carried out, write by a source side injection method is carried out while applying a negative voltage to the p type well region via the well line.

Abstract translation: 在通过热载流子注入进行重写的分闸门MONOS存储器中，保持特性得到改善。 存储单元的选择栅电极连接到选择栅极线，并且存储栅电极连接到存储栅极线。 漏极区域连接到位线，并且源极区域连接到源极线。 此外，阱线连接到其中形成存储单元的p型阱区域。 当要对存储单元进行写入时，通过源极侧注入方法进行写入，同时通过阱线向p型阱区域施加负电压。

公开(公告)号：US07915666B2

公开(公告)日：2011-03-29

申请号：US12124143

申请日：2008-05-20

Applicant: Kan Yasui ,  Tetsuya Ishimaru ,  Digh Hisamoto ,  Yasuhiro Shimamoto

Inventor： Kan Yasui ,  Tetsuya Ishimaru ,  Digh Hisamoto ,  Yasuhiro Shimamoto

IPC: H01L29/792

CPC classification number: H01L29/792 ,  G11C16/0425 ,  G11C16/10 ,  H01L27/11526 ,  H01L27/11546 ,  H01L29/42344

Abstract: An erase method where a corner portion on which an electric field concentrates locally is provided on the memory gate electrode, and charges in the memory gate electrode are injected into a charge trap film in a gate dielectric with Fowler-Nordheim tunneling operation is used. Since current consumption at the time of erase can be reduced by the Fowler-Nordheim tunneling, a power supply circuit area of a memory module can be reduced. Since write disturb resistance can be improved, a memory array area can be reduced by adopting a simpler memory array configuration. Owing to both the effects, an area of the memory module can be largely reduced, so that manufacturing cost can be reduced. Further, since charge injection centers of write and erase coincide with each other, so that (program and erase) endurance is improved.

Abstract translation: 在存储栅电极上设置有局部集中电场的角部的擦除方法，并且使用Fowler-Nordheim隧道操作将存储栅电极中的电荷注入栅极电介质中的电荷陷阱膜。 由于通过Fowler-Nordheim隧道可以减少擦除时的电流消耗，因此可以减少存储器模块的电源电路区域。 由于可以提高写入干扰电阻，所以可以通过采用更简单的存储器阵列配置来减少存储器阵列区域。 由于这两个效果，可以大大减少存储器模块的面积，从而可以降低制造成本。 此外，由于写入和擦除的电荷注入中心彼此一致，所以（编程和擦除）耐久性得到改善。

公开(公告)号：US20110039385A1

公开(公告)日：2011-02-17

申请号：US12912609

申请日：2010-10-26

Applicant: Yasuhiro Shimamoto ,  Digh Hisamoto ,  Tetsuya Ishimaru ,  Shinichiro Kimura

Inventor： Yasuhiro Shimamoto ,  Digh Hisamoto ,  Tetsuya Ishimaru ,  Shinichiro Kimura

IPC: H01L21/336

CPC classification number: H01L29/792 ,  G11C16/0425 ,  H01L21/28282 ,  H01L21/31155 ,  H01L27/105 ,  H01L27/11521 ,  H01L27/11526 ,  H01L27/11546 ,  H01L27/11568 ,  H01L29/42344 ,  H01L29/66833

Abstract: Performance and reliability of a semiconductor device including a non-volatile memory are improved. A memory cell of the non-volatile memory includes, over an upper portion of a semiconductor substrate, a select gate electrode formed via a first dielectric film and a memory gate electrode formed via a second dielectric film formed of an ONO multilayered film having a charge storing function. The first dielectric film functions as a gate dielectric film, and includes a third dielectric film made of silicon oxide or silicon oxynitride and a metal-element-containing layer made of a metal oxide or a metal silicate formed between the select gate electrode and the third dielectric film. A semiconductor region positioned under the memory gate electrode and the second dielectric film has a charge density of impurities lower than that of a semiconductor region positioned under the select gate electrode and the first dielectric film.

Abstract translation: 提高了包括非易失性存储器的半导体器件的性能和可靠性。 非易失性存储器的存储单元包括在半导体衬底的上部上的经由第一电介质膜形成的选择栅电极和通过由具有电荷的ONO多层膜形成的第二电介质膜形成的存储栅电极 存储功能。 第一介质膜用作栅极电介质膜，并且包括由氧化硅或氮氧化硅制成的第三电介质膜和由选择栅电极和第三电极之间形成的金属氧化物或金属硅酸盐构成的含金属元素层 电介质膜。 位于存储栅电极下方的半导体区域和第二电介质膜的电荷密度低于位于选择栅电极和第一电介质膜下方的半导体区域的电荷密度。

公开(公告)号：US07847331B2

公开(公告)日：2010-12-07

申请号：US11030900

申请日：2005-01-10

Applicant: Tetsuya Ishimaru ,  Digh Hisamoto ,  Kan Yasui ,  Shinichiro Kimura

Inventor： Tetsuya Ishimaru ,  Digh Hisamoto ,  Kan Yasui ,  Shinichiro Kimura

IPC: H01L29/792

CPC classification number: G11C16/0466 ,  H01L21/28282 ,  H01L29/66833 ,  H01L29/792

Abstract: In a situation where a memory cell includes an ONO film, which comprises a silicon nitride film for charge storage and oxide films positioned above and below the silicon nitride film; a memory gate above the ONO film; a select gate, which is adjacent to a lateral surface of the memory gate via the ONO film; a gate insulator positioned below the select gate; a source region; and a drain region, an erase operation is performed by injecting holes generated by BTBT into the silicon nitride film while applying a positive potential to the source region, applying a negative potential to the memory gate, applying a positive potential to the select gate, and flowing a current from the drain region to the source region, thus improving the characteristics of a nonvolatile semiconductor memory device.

Abstract translation: 在存储单元包括ONO膜的情况下，其包括用于电荷存储的氮化硅膜和位于氮化硅膜上方和下方的氧化膜; 在ONO电影上方的记忆门; 选择栅极，其经由ONO膜与存储栅的侧表面相邻; 位于选择门下方的栅极绝缘体; 源区; 和漏极区域，通过将BTBT产生的空穴注入氮化硅膜，同时向源极区域施加正电位，向存储栅极施加负电位，向选择栅极施加正电位，进行擦除操作，以及 使电流从漏极区域流向源极区域，从而改善非易失性半导体存储器件的特性。

公开(公告)号：US07709315B2

公开(公告)日：2010-05-04

申请号：US11773842

申请日：2007-07-05

Applicant: Naoki Tega ,  Hiroshi Miki ,  Yasuhiro Shimamoto ,  Digh Hisamoto ,  Tetsuya Ishimaru

Inventor： Naoki Tega ,  Hiroshi Miki ,  Yasuhiro Shimamoto ,  Digh Hisamoto ,  Tetsuya Ishimaru

IPC: H01L21/8238

CPC classification number: H01L29/792 ,  B82Y10/00 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11568 ,  H01L27/11573 ,  H01L29/42324 ,  H01L29/4234 ,  H01L29/42344 ,  H01L29/66833

Abstract: An interface between a bottom oxide film and a silicon nitride film in a neighborhood of a bottom part of a select gate is located at a position as high as or higher than that of an interface between a silicon substrate (p-type well) and a gate insulating film (d≧0) Further, the gate insulating film and the bottom oxide film are successively and smoothly jointed in the neighborhood of the bottom part of the select gate. By this configuration, localization in a distribution of electrons injected into the silicon nitride film in the writing is mitigated and electrons to be left unerased by hot-hole erasing are reduced. Therefore, not only the increase ratio of the electrons left unerased in the writing can be reduced, but also the problem in which the threshold voltage does not decrease to the predetermined voltage in the deletion can be suppressed.

Abstract translation: 在选择栅极的底部附近的底部氧化物膜和氮化硅膜之间的界面位于硅衬底（p型阱）和硅衬底（p型阱）之间的界面的高度或更高的位置 栅极绝缘膜（d≥0）此外，栅极绝缘膜和底部氧化物膜在选择栅极的底部附近依次平滑地接合。 通过这种配置，减轻了在写入中注入到氮化硅膜中的电子分布中的定位，并且减少了通过热孔擦除而未被消除的电子。 因此，不仅可以减少在写入时未加电的电子的增加比例，还可以抑制在删除中阈值电压不降低到预定电压的问题。

公开(公告)号：US07667259B2

公开(公告)日：2010-02-23

申请号：US11452256

申请日：2006-06-14

Applicant: Kan Yasui ,  Digh Hisamoto ,  Tetsuya Ishimaru ,  Shin-Ichiro Kimura

Inventor： Kan Yasui ,  Digh Hisamoto ,  Tetsuya Ishimaru ,  Shin-Ichiro Kimura

IPC: H01L21/00

CPC classification number: H01L27/115 ,  G11C16/0425 ,  H01L27/11568 ,  H01L29/42344

Abstract: A method of manufacturing a non-volatile semiconductor memory device is provided which overcomes a problem of penetration of implanted ions due to the difference of an optimal gate height in simultaneous formation of a self-align split gate type memory cell utilizing a side wall structure and a scaled MOS transistor. A select gate electrode to form a side wall in a memory area is formed to be higher than that of the gate electrode in a logic area so that the height of the side wall gate electrode of the self-align split gate memory cell is greater than that of the gate electrode in the logic area. Height reduction for the gate electrode is performed in the logic area before gate electrode formation.

Abstract translation: 提供了一种制造非易失性半导体存储器件的方法，其克服了由于利用侧壁结构同时形成自对准分裂栅型存储单元而产生的最佳栅极高度的差异而引入的注入离子的问题，以及 一个缩放的MOS晶体管。 形成在存储区域中形成侧壁的选择栅电极比逻辑区域中的栅电极高，使得自对准分离栅极存储单元的侧壁栅电极的高度大于 在逻辑区域的栅电极。 栅极电极的高度降低在栅电极形成之前的逻辑区域中进行。