公开(公告)号：US08722511B2

公开(公告)日：2014-05-13

申请号：US13154754

申请日：2011-06-07

Applicant: Ralf Richter ,  Peter Javorka ,  Kai Frohberg

Inventor： Ralf Richter ,  Peter Javorka ,  Kai Frohberg

IPC: H01L21/76

CPC classification number: H01L23/485 ,  H01L21/76834 ,  H01L21/76837 ,  H01L21/823412 ,  H01L21/823425 ,  H01L21/823481 ,  H01L21/823807 ,  H01L21/823878 ,  H01L29/7846 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Contact failures in sophisticated semiconductor devices may be reduced by relaxing the pronounced surface topography in isolation regions prior to depositing the interlayer dielectric material system. To this end, a deposition/etch sequence may be applied in which a fill material may be removed from the active region, while the recesses in the isolation regions may at least be partially filled.

Abstract translation: 复杂的半导体器件中的接触故障可以通过在沉积层间绝缘材料系统之前放宽隔离区域中显着的表面形貌来降低。 为此，可以施加沉积/蚀刻顺序，其中填充材料可以从有源区域移除，而隔离区域中的凹部可以至少部分地被填充。

公开(公告)号：US08642419B2

公开(公告)日：2014-02-04

申请号：US13400407

申请日：2012-02-20

Applicant: Stephan Kronholz ,  Jorg Radecker ,  Hans-Juergen Thees ,  Peter Javorka

Inventor： Stephan Kronholz ,  Jorg Radecker ,  Hans-Juergen Thees ,  Peter Javorka

IPC: H01L21/8238

CPC classification number: H01L21/76232

Abstract: Disclosed herein are various methods of forming isolation structures, such as trench isolation structures, for semiconductor devices. In one example, the method includes forming a trench in a semiconducting substrate, forming a lower isolation structure in the trench, wherein the lower isolation structure has an upper surface that is below an upper surface of the substrate, and forming an upper isolation structure above the lower isolation structure, wherein a portion of the upper isolation structure is positioned within the trench.

Abstract translation: 本文公开了形成用于半导体器件的隔离结构，例如沟槽隔离结构的各种方法。 在一个示例中，该方法包括在半导体衬底中形成沟槽，在沟槽中形成较低的隔离结构，其中下部隔离结构具有位于衬底上表面下方的上表面，并且形成上部隔离结构 所述下隔离结构，其中所述上隔离结构的一部分位于所述沟槽内。

公开(公告)号：US08481381B2

公开(公告)日：2013-07-09

申请号：US13232711

申请日：2011-09-14

Applicant: Stephan-Detlef Kronholz ,  Peter Javorka ,  Maciej Wiatr

Inventor： Stephan-Detlef Kronholz ,  Peter Javorka ,  Maciej Wiatr

IPC: H01L21/336 ,  H01L21/8234

CPC classification number: H01L22/10 ,  H01L21/823807 ,  H01L21/823842 ,  H01L21/823871 ,  H01L21/823878 ,  H01L29/7848 ,  Y02P80/30

Abstract: When forming high-k metal gate electrode structures in a semiconductor device on the basis of a basic transistor design, undue exposure of sensitive materials at end portions of the gate electrode structures of N-channel transistors may be avoided, for instance, prior to and upon incorporating a strain-inducing semiconductor material into the active region of P-channel transistors, thereby contributing to superior production yield for predefined transistor characteristics and performance.

Abstract translation: 在基于晶体管的基础上在半导体器件中形成高k金属栅极电极结构时，可以避免在N沟道晶体管的栅电极结构的端部处敏感材料的过度曝光，例如，在 在将应变诱导半导体材料并入P沟道晶体管的有源区域中，从而有助于提高预定晶体管特性和性能的产量。

公开(公告)号：US20130052819A1

公开(公告)日：2013-02-28

申请号：US13218089

申请日：2011-08-25

Applicant: Thilo Scheiper ,  Peter Javorka ,  Stefan Flachowsky ,  Clemens Fitz

Inventor： Thilo Scheiper ,  Peter Javorka ,  Stefan Flachowsky ,  Clemens Fitz

IPC: H01L21/3205

CPC classification number: H01L21/28518 ,  H01L21/823814 ,  H01L21/823835

Abstract: Disclosed herein are various methods of forming metal silicide regions on semiconductor devices by using different temperatures during the silicidation processes. In one example, the method includes forming a plurality of N-doped source/drain regions and a plurality of P-doped source/drain regions in a semiconducting substrate and performing a first heating process at a first temperature to initially form a first metal silicide region in each of the P-doped source/drain regions. The method further includes performing a second heating process at a second temperature to initially form a second metal silicide region in each of the N-doped source/drain regions, wherein the second temperature is less than the first temperature and performing a third heating process at a third temperature to complete the formation of the first and second metal silicide regions, wherein the third temperature is greater than the first temperature.

Abstract translation: 本文公开了通过在硅化工艺期间使用不同温度在半导体器件上形成金属硅化物区域的各种方法。 在一个示例中，该方法包括在半导体衬底中形成多个N掺杂源极/漏极区域和多个P掺杂的源极/漏极区域，并且在第一温度下执行第一加热过程以最初形成第一金属硅化物 每个P掺杂源/漏区中的区域。 该方法还包括在第二温度下执行第二加热处理，以在N掺杂源极/漏极区域中的每一个中初始形成第二金属硅化物区域，其中第二温度小于第一温度，并且在 第三温度以完成所述第一和第二金属硅化物区域的形成，其中所述第三温度大于所述第一温度。

公开(公告)号：US08377786B2

公开(公告)日：2013-02-19

申请号：US13020369

申请日：2011-02-03

Applicant: Stephan-Detlef Kronholz ,  Peter Javorka ,  Roman Boschke

Inventor： Stephan-Detlef Kronholz ,  Peter Javorka ,  Roman Boschke

IPC: H01L21/311 ,  H01L21/3115

CPC classification number: H01L21/31155 ,  H01L21/31111 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823468 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823864

Abstract: Embodiments of methods for fabricating the semiconductor devices are provided. The method includes forming a layer of spacer material over a semiconductor region that includes a first gate electrode structure and a second gate electrode structure. Carbon is introduced into a portion of the layer covering the semiconductor region about the first gate electrode structure or the second gate electrode structure. The layer is etched to form a first sidewall spacer about the first gate electrode structure and a second sidewall spacer about the second gate electrode structure.

Abstract translation: 提供了制造半导体器件的方法的实施例。 该方法包括在包括第一栅电极结构和第二栅电极结构的半导体区上形成间隔物层。 将碳引入围绕第一栅电极结构或第二栅电极结构覆盖半导体区的层的一部分。 蚀刻该层以围绕第一栅极电极结构形成第一侧壁隔离物，并围绕第二栅电极结构形成第二侧壁隔离物。

公开(公告)号：US08274120B2

公开(公告)日：2012-09-25

申请号：US12710744

申请日：2010-02-23

Applicant: Andy Wei ,  Thorsten Kammler ,  Jan Hoentschel ,  Manfred Horstmann ,  Peter Javorka ,  Joe Bloomquist

Inventor： Andy Wei ,  Thorsten Kammler ,  Jan Hoentschel ,  Manfred Horstmann ,  Peter Javorka ,  Joe Bloomquist

IPC: H01L29/76 ,  H01L29/94

CPC classification number: H01L29/66628 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/1083 ,  H01L29/165 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/66772 ,  H01L29/66787 ,  H01L29/7843 ,  H01L29/7848 ,  H01L29/78621 ,  H01L29/78684

Abstract: By recessing drain and source regions, a highly stressed layer, such as a contact etch stop layer, may be formed in the recess in order to enhance the strain generation in the adjacent channel region of a field effect transistor. Moreover, a strained semiconductor material may be positioned in close proximity to the channel region by reducing or avoiding undue relaxation effects of metal silicides, thereby also providing enhanced efficiency for the strain generation. In some aspects, both effects may be combined to obtain an even more efficient strain-inducing mechanism.

Abstract translation: 通过凹陷漏极和源极区域，可以在凹部中形成诸如接触蚀刻停止层的高应力层，以增强场效应晶体管的相邻沟道区域中的应变产生。 此外，应变半导体材料可以通过减少或避免金属硅化物的不适当的松弛效应来定位在靠近沟道区域，从而也为应变产生提供增强的效率。 在一些方面，两种效应可以组合以获得更有效的应变诱导机制。

公开(公告)号：US20120235249A1

公开(公告)日：2012-09-20

申请号：US13421394

申请日：2012-03-15

Applicant: Stephan-Detlef Kronholz ,  Peter Javorka ,  Maciej Wiatr

Inventor： Stephan-Detlef Kronholz ,  Peter Javorka ,  Maciej Wiatr

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L21/84 ,  H01L21/76283 ,  H01L21/823412 ,  H01L21/823481 ,  H01L21/823807 ,  H01L21/823878 ,  H01L27/1203

Abstract: When forming sophisticated high-k metal gate electrode structures on the basis of a threshold voltage adjusting semiconductor alloy, a highly efficient in situ process technique may be applied in order to form a recess in dedicated active regions and refilling the recess with a semiconductor alloy. In order to reduce or avoid etch-related irregularities during the recessing of the active regions, the degree of aluminum contamination during the previous processing, in particular during the formation of the trench isolation regions, may be controlled.

Abstract translation: 当基于阈值电压调节半导体合金形成复杂的高k金属栅电极结构时，可以应用高效的原位工艺技术，以便在专用有源区域中形成凹槽并用半导体合金再填充凹槽。 为了在活性区域的凹陷期间减少或避免蚀刻相关的不规则性，可以控制在先前处理期间，特别是在形成沟槽隔离区域期间的铝污染程度。

公开(公告)号：US20120025318A1

公开(公告)日：2012-02-02

申请号：US13154754

申请日：2011-06-07

Applicant: Ralf Richter ,  Peter Javorka ,  Kai Frohberg

Inventor： Ralf Richter ,  Peter Javorka ,  Kai Frohberg

IPC: H01L27/088 ,  H01L21/336

CPC classification number: H01L23/485 ,  H01L21/76834 ,  H01L21/76837 ,  H01L21/823412 ,  H01L21/823425 ,  H01L21/823481 ,  H01L21/823807 ,  H01L21/823878 ,  H01L29/7846 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Contact failures in sophisticated semiconductor devices may be reduced by relaxing the pronounced surface topography in isolation regions prior to depositing the interlayer dielectric material system. To this end, a deposition/etch sequence may be applied in which a fill material may be removed from the active region, while the recesses in the isolation regions may at least be partially filled.

Abstract translation: 复杂的半导体器件中的接触故障可以通过在沉积层间绝缘材料系统之前放宽隔离区域中显着的表面形貌来降低。 为此，可以施加沉积/蚀刻顺序，其中填充材料可以从有源区域移除，而隔离区域中的凹部可以至少部分地被填充。

公开(公告)号：US08039338B2

公开(公告)日：2011-10-18

申请号：US12397574

申请日：2009-03-04

Applicant: Manfred Horstmann ,  Peter Javorka ,  Karsten Wieczorek ,  Kerstin Ruttloff

Inventor： Manfred Horstmann ,  Peter Javorka ,  Karsten Wieczorek ,  Kerstin Ruttloff

IPC: H01L21/8238

CPC classification number: H01L21/823842 ,  H01L21/823871

Abstract: By incorporating nitrogen into the P-doped regions and N-doped regions of the gate electrode material prior to patterning the gate electrode structure, yield losses due to reactive wet chemical cleaning processes may be significantly reduced.

Abstract translation: 通过在对栅电极结构进行构图之前将氮掺入P掺杂区域和栅极电极材料的N掺杂区域中，可以显着降低由于反应性湿化学清洗过程引起的屈服损失。

公开(公告)号：US20110156172A1

公开(公告)日：2011-06-30

申请号：US12908053

申请日：2010-10-20

Applicant: Stephan Kronholz ,  Maciej Wiatr ,  Roman Boschke ,  Peter Javorka

Inventor： Stephan Kronholz ,  Maciej Wiatr ,  Roman Boschke ,  Peter Javorka

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L21/84 ,  H01L21/823807 ,  H01L21/823842 ,  H01L27/1203 ,  H01L29/1054 ,  H01L29/517 ,  H01L29/66651

Abstract: When forming sophisticated gate electrode structures requiring a threshold adjusting semiconductor alloy for one type of transistor, a recess is formed in the corresponding active region, thereby providing superior process uniformity during the deposition of the semiconductor material. Moreover, the well dopant species is implanted after the recessing, thereby avoiding undue dopant loss. Due to the recess, any exposed sidewall surface areas of the active region may be avoided during the selective epitaxial growth process, thereby significantly contributing to enhanced threshold stability of the resulting transistor including the high-k metal gate stack.

Abstract translation: 当形成需要用于一种类型的晶体管的阈值调节半导体合金的复杂的栅电极结构时，在相应的有源区中形成凹部，从而在半导体材料的沉积期间提供优异的工艺均匀性。 此外，在凹陷之后注入阱掺杂剂物质，从而避免不必要的掺杂剂损失。 由于凹槽，可以在选择性外延生长工艺期间避免有源区的任何暴露的侧壁表面区域，从而显着地有助于提高包括高k金属栅叠层的晶体管的阈值稳定性。