公开(公告)号：US20130057312A1

公开(公告)日：2013-03-07

申请号：US13579562

申请日：2011-02-16

申请人： Alberto Pagani

发明人： Alberto Pagani

IPC分类号： H01L23/58 ,  G01R31/26

CPC分类号： G01R31/275 ,  G01R31/2853 ,  H01L21/76898 ,  H01L22/34 ,  H01L23/481 ,  H01L2924/0002 ,  H01L2924/00

摘要： An embodiment of a testing system for carrying out electrical testing of at least one first through via extending, at least in part, through a substrate of a first body of semiconductor material. The testing system has a first electrical test circuit integrated in the first body and electrically coupled to the first through via and to electrical-connection elements carried by the first body for electrical connection towards the outside; the first electrical test circuit enables detection of at least one electrical parameter of the first through via through the electrical-connection elements.

摘要翻译： 用于进行至少一个第一通孔的电测试的测试系统的实施例，所述至少一个第一通孔至少部分地延伸穿过第一半导体材料体的衬底。 测试系统具有集成在第一主体中并与第一通孔电耦合的第一电测试电路和由第一主体携带的电连接元件，用于电连接到外部; 第一电测试电路使得能够通过电连接元件检测第一通孔的至少一个电参数。

公开(公告)号：US20130027071A1

公开(公告)日：2013-01-31

申请号：US13558210

申请日：2012-07-25

申请人： Roberto Canegallo ,  Mauro Scandiuzzo ,  Roberto Cardu ,  Eleonora Franchi Scarselli ,  Alberto Pagani

发明人： Roberto Canegallo ,  Mauro Scandiuzzo ,  Roberto Cardu ,  Eleonora Franchi Scarselli ,  Alberto Pagani

IPC分类号： G01R31/302

CPC分类号： G01R31/2889 ,  G01R31/3025

摘要： A testing apparatus includes a tester and a probe card system that includes a probe card connected to the tester, and an active interposer connected to the probe card and wirelessly coupled with a device to be tested. The active interposer includes pads positioned on its free surface facing the device. The pads are positioned with respect to pads of the device so that each pad of the active interposer faces a pad of the device and is separated therefrom by a dielectric. Each pair of facing pads forms an elementary wireless coupling element which allows a wireless transmission between the active interposer and the device. The active interposer also includes an amplifier circuit configured to amplify wireless signals from the device before forwarding them to the tester. The probe card system includes a transmission element able to transmit a power voltage from the tester to the device.

摘要翻译： 测试装置包括测试器和探针卡系统，其包括连接到测试器的探针卡，以及连接到探针卡并与要测试的设备无线耦合的有源插入器。 有源插入器包括位于其面向设备的自由表面上的焊盘。 焊盘相对于器件的焊盘定位，使得有源插入器的每个焊盘面向器件的焊盘并且通过电介质与其分离。 每对相对的焊盘形成基本无线耦合元件，其允许在有源插入器和设备之间进行无线传输。 有源插入器还包括放大器电路，其被配置为在将它们转发到测试器之前放大来自器件的无线信号。 探针卡系统包括能够从测试仪向设备传输电力电压的传输元件。

公开(公告)号：US20130026466A1

公开(公告)日：2013-01-31

申请号：US13554133

申请日：2012-07-20

申请人： Alberto PAGANI

发明人： Alberto PAGANI

IPC分类号： H01L23/544 ,  H01L21/768 ,  H01L29/02 ,  H01L23/525

CPC分类号： G01R31/2884 ,  H01L22/32 ,  H01L22/34 ,  H01L23/585 ,  H01L24/05 ,  H01L2224/02166 ,  H01L2224/05093 ,  H01L2224/05554 ,  H01L2924/12042 ,  H01L2924/00

摘要： An embodiment of a testing architecture of integrated circuits on a wafer is described of the type including at least one first circuit of a structure TEG realized in a scribe line providing separation between at least one first and one second integrated circuit. The architecture includes at least one pad shared by a second circuit inside at least one of these first and second integrated circuit and the first circuit, as well as a switching circuitry coupled to the at least one pad and to these first and second circuits.

摘要翻译： 描述了晶片上的集成电路的测试架构的实施例，其包括在划线中实现的结构TEG的至少一个第一电路，其提供至少一个第一和第二集成电路之间的间隔。 该架构包括在这些第一和第二集成电路和第一电路中的至少一个内的第二电路共享的至少一个焊盘，以及耦合到至少一个焊盘和这些第一和第二电路的开关电路。

公开(公告)号：US08358147B2

公开(公告)日：2013-01-22

申请号：US12982753

申请日：2010-12-30

申请人： Alberto Pagani

发明人： Alberto Pagani

IPC分类号： G01R31/02

CPC分类号： G01R31/31905 ,  G01R31/3172 ,  G01R31/31926

摘要： A method of testing integrated circuits is provided. The method includes establishing at least one first physical communication channel between a test equipment and a respective group of integrated circuits under test by having probes of the test equipment contacting at least one corresponding physical contact terminal of each integrated circuit of the respective group. The method further includes having the test equipment exchanging, over the at least one first physical communication channel, the same test stimuli with each integrated circuit of the group. The method still further includes having each integrated circuit of the group establishing a corresponding second physical communication channel with the test equipment by having at least one physical contact terminal of the integrated circuit contacted by a corresponding probe of the test equipment. The method further includes having each integrated circuit of the group exchanging, over the second physical communication channel, a corresponding test response signal based on the received test stimuli with the test equipment. The test stimuli are exchanged by modulating at least one first carrier wave based on the test stimuli; the at least one first carrier wave has at least one first frequency. The test response signals of each integrated circuit of the group are exchanged by modulating at least one respective second carrier wave based on the test response signals; each second carrier wave have at least one respective second frequency.

摘要翻译： 提供了一种测试集成电路的方法。 该方法包括通过使测试设备的探针接触相应组的每个集成电路的至少一个对应的物理接触端，来建立测试设备与被测试的相应组的集成电路之间的至少一个第一物理通信信道。 所述方法还包括使所述测试设备在所述至少一个第一物理通信信道中与所述组的每个集成电路交换相同的测试刺激。 该方法还包括使该组的每个集成电路与测试设备建立相应的第二物理通信信道，其中该集成电路的至少一个物理接触端子与测试设备的相应探针接触。 该方法还包括使得该组的每个集成电路在第二物理通信信道上基于所接收的与测试设备的测试刺激相交换的测试响应信号。 通过基于测试刺激调制至少一个第一载波来交换测试刺激; 所述至少一个第一载波具有至少一个第一频率。 通过基于测试响应信号调制至少一个相应的第二载波来交换该组的每个集成电路的测试响应信号; 每个第二载波具有至少一个相应的第二频率。

公开(公告)号：US20120081137A1

公开(公告)日：2012-04-05

申请号：US13252895

申请日：2011-10-04

申请人： Alberto Pagani ,  Jean-Michel Bard

发明人： Alberto Pagani ,  Jean-Michel Bard

IPC分类号： G01R31/00

CPC分类号： G06F11/26

摘要： A testing method is described of at least one device provided with an integrated testing circuit and in communication with at least one tester where messages/instructions/test signals/information are exclusively sent from the tester to the device . A testing architecture is also described for implementing this testing method.

摘要翻译： 描述了至少一个设置有集成测试电路并且与至少一个测试器进行通信的测试方法，其中消息/指令/测试信号/信息从测试仪专门发送到设备。 还描述了用于实现该测试方法的测试架构。

公开(公告)号：US20120025344A1

公开(公告)日：2012-02-02

申请号：US13194197

申请日：2011-07-29

申请人： Alberto PAGANI

发明人： Alberto PAGANI

IPC分类号： H01L21/76 ,  H01L29/06 ,  H01L27/02

CPC分类号： H01L23/544 ,  H01L21/268 ,  H01L21/3212 ,  H01L21/7684 ,  H01L21/7685 ,  H01L21/76877 ,  H01L23/53238 ,  H01L23/562 ,  H01L23/585 ,  H01L2223/54406 ,  H01L2223/54413 ,  H01L2223/54433 ,  H01L2223/54473 ,  H01L2223/5448 ,  H01L2924/0002 ,  H01L2924/00

摘要： An embodiment of a method for producing traceable integrated circuits includes forming on a wafer of semiconductor material functional regions for implementing specific functionalities of corresponding integrated circuits, forming at least one seal ring around each functional region of the corresponding integrated circuit, and forming on each integrated circuit at least one marker indicative of information of the integrated circuit. Forming on each integrated circuit at least one marker may include forming the at least one marker on at least a portion of the respective seal ring that is visible.

摘要翻译： 制造可追溯集成电路的方法的一个实施例包括在半导体材料功能区的晶片上形成用于实现相应的集成电路的特定功能，在相应的集成电路的每个功能区周围形成至少一个密封环，以及在每个集成电路 电路指示集成电路的信息的至少一个标记。 在每个集成电路上形成至少一个标记可以包括在可见的相应密封环的至少一部分上形成至少一个标记。

公开(公告)号：US20110279137A1

公开(公告)日：2011-11-17

申请号：US13106615

申请日：2011-05-12

申请人： Alberto PAGANI

发明人： Alberto PAGANI

IPC分类号： G01R1/067 ,  G01R3/00 ,  G01R31/20

CPC分类号： G01R3/00 ,  G01R1/06761 ,  G01R1/07307 ,  G01R1/07342 ,  G01R31/31905 ,  Y10T29/49002

摘要： An embodiment of a method is proposed for producing cantilever probes for use in a test apparatus of integrated electronic circuits; the probes are configured to contact during the test corresponding terminals of the electronic circuits to be tested. An embodiment comprises forming probe bodies of electrically conductive materials. In an embodiment, the method further includes forming on a lower portion of each probe body that, in use, is directed to the respective terminal to be contacted, an electrically conductive contact region having a first hardness value equal to or greater than 300 HV; each contact region and the respective probe body form the corresponding probe.

摘要翻译： 提出了一种用于制造用于集成电子电路的测试装置的悬臂探针的方法的实施例; 探针被配置为在测试的电子电路的相应端子的测试期间接触。 一个实施例包括形成导电材料的探针体。 在一个实施例中，该方法还包括在每个探针体的下部形成在使用中的，被引导到要接触的相应端子的第一硬度值等于或大于300HV的导电接触区域; 每个接触区域和相应的探针体形成相应的探针。

公开(公告)号：US20110278568A1

公开(公告)日：2011-11-17

申请号：US13106557

申请日：2011-05-12

申请人： Alberto PAGANI

发明人： Alberto PAGANI

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L21/66 ,  H01L29/66

CPC分类号： H01L22/32 ,  G01R31/2886 ,  H01L21/76877 ,  H01L23/528 ,  H01L23/53209 ,  H01L23/53242 ,  H01L23/53257 ,  H01L24/05 ,  H01L24/92 ,  H01L2224/04042 ,  H01L2224/05082 ,  H01L2224/05144 ,  H01L2224/05155 ,  H01L2224/05157 ,  H01L2224/05164 ,  H01L2224/05173 ,  H01L2224/05557 ,  H01L2224/05644 ,  H01L2224/05664 ,  H01L2224/48463 ,  H01L2924/01013 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01045 ,  H01L2924/01046 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/19041 ,  H01L2924/00014 ,  H01L2924/00

摘要： An embodiment of a manufacturing process of an integrated electronic circuit is proposed; the process comprises forming a substrate comprising a plurality of functional components of the electronic circuit, creating a plurality of conductive layers on such substrate to form an electric contact region with high hardness equal to or greater than a first hardness value of about 300 HV, contacting the electric contact region with a probe and running an electric test of the electronic circuit. In an embodiment, the process further comprises, after the test run, creating a covering conductive layer on at least one part of the electric contact region contacted by the probe.

摘要翻译： 提出了集成电子电路的制造过程的实施例; 该方法包括形成包括电子电路的多个功能部件的基板，在该基板上形成多个导电层，以形成具有等于或大于约300HV的第一硬度值的高硬度的电接触区域， 电接触区域与探头并运行电子电路的电气测试。 在一个实施例中，该方法还包括在测试运行之后，在由探针接触的电接触区域的至少一部分上形成覆盖导电层。

公开(公告)号：US20110202799A1

公开(公告)日：2011-08-18

申请号：US13027617

申请日：2011-02-15

申请人： Alberto Pagani

发明人： Alberto Pagani

IPC分类号： G06F11/00

CPC分类号： G01R31/31908 ,  G01R31/3025 ,  G01R31/318572 ,  H01L2224/16145 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/73265 ,  H01L2924/13091 ,  H01L2924/15311 ,  H01L2924/00014 ,  H01L2924/00

摘要： The disclosure relates to a process for making an electric testing of electronic devices DUT, of the type comprising the steps of: connecting at least one electronic device DUT to an automatic testing apparatus or ATE apparatus suitable for making the testing of digital circuits; sending, through said ATE apparatus, control signals for the electric testing to said electronic device DUT. Advantageously, the process also comprises the steps of: making the electric testing of said electronic device DUT through at least one reconfigurable digital interface RDI connected to said ATE apparatus through a dedicated digital communication channel and comprising a limited number of communication or connection lines strictly appointed to the exchange of the testing information; and sending from said electronic device DUT to said ATE apparatus response messages, if any, containing measures, failure information and data in response to said control signals and through said digital communication channel.

摘要翻译： 本公开涉及一种用于进行电子设备DUT的电测试的方法，其类型包括以下步骤：将至少一个电子设备DUT连接到适于进行数字电路测试的自动测试设备或ATE设备; 通过所述ATE装置向所述电子设备DUT发送用于电测试的控制信号。 有利地，该方法还包括以下步骤：通过专用数字通信信道通过至少一个可连接到所述ATE设备的可重构数字接口RDI进行所述电子设备DUT的电测试，并且包括有限数量的通信或连接线 交换测试信息; 以及响应于所述控制信号并通过所述数字通信信道，从所述电子设备DUT向所述ATE设备发送包含测量，故障信息和数据的响应消息（如果有的话）。

公开(公告)号：US20110156732A1

公开(公告)日：2011-06-30

申请号：US12974957

申请日：2010-12-21

申请人： Alberto PAGANI

发明人： Alberto PAGANI

IPC分类号： G01R31/00

CPC分类号： G01R31/2884 ,  G01R31/2889 ,  G01R31/2891

摘要： An embodiment for making a check of the electric type executed on wafer for testing the correct positioning or alignment of the probes of a probe card on the pads or bumps of the electronic devices integrated on semiconductor wafer. An embodiment consists in making a current circulate in at least part of the seal ring of at least one of the above devices, and in case it has to flow in the seal ring of more devices, these seal rings are suitably interconnected to each other. Thanks to an embodiment the seal ring may also be reinforced in the angle areas of the chip, and suitable circuits may be possibly inserted in the seal ring or between the seal rings.

摘要翻译： 用于检查在晶片上执行的电气类型的实施例，用于测试探针卡的探针在集成在半导体晶片上的电子器件的焊盘或凸块上的正确定位或对准。 一个实施例在于使电流在上述装置中的至少一个的密封环的至少一部分中循环，并且在其必须在更多装置的密封环中流动的情况下，这些密封环适当地彼此互连。 由于实施例，密封环也可以在芯片的角度区域中被加强，并且合适的电路可能可能插入密封环中或密封环之间。