公开(公告)号：US20080113499A1

公开(公告)日：2008-05-15

申请号：US12003559

申请日：2007-12-28

Applicant: Kozo Makiyama ,  Naoya Ikechi ,  Takahiro Tan

Inventor： Kozo Makiyama ,  Naoya Ikechi ,  Takahiro Tan

IPC: H01L21/3205

CPC classification number: H01L21/0274 ,  H01L21/28114 ,  H01L21/28264 ,  H01L21/28587 ,  H01L29/42316 ,  H01L29/42376 ,  H01L29/517 ,  H01L29/66462 ,  H01L29/66871 ,  H01L29/78 ,  Y10S430/143 ,  Y10S438/949 ,  Y10S438/95 ,  Y10S438/951

Abstract: A semiconductor device has: a semiconductor substrate having a pair of current input/output regions via which current flows; an insulating film formed on the semiconductor substrate and having a gate electrode opening; and a mushroom gate electrode structure formed on the semiconductor substrate via the gate electrode opening, the mushroom gate electrode structure having a stem and a head formed on the stem, the stem having a limited size on the semiconductor substrate along a current direction and having a forward taper shape upwardly and monotonically increasing the size along the current direction, the head having a size expanded stepwise along the current direction, and the stem contacting the semiconductor substrate in the gate electrode opening and riding the insulating film near at a position of at least one of opposite ends of the stem along the current direction.

公开(公告)号：US07335542B2

公开(公告)日：2008-02-26

申请号：US11713599

申请日：2007-03-05

Applicant: Kozo Makiyama ,  Naoya Ikechi ,  Takahiro Tan

Inventor： Kozo Makiyama ,  Naoya Ikechi ,  Takahiro Tan

IPC: H01L21/338 ,  H01L21/44

CPC classification number: H01L21/0274 ,  H01L21/28114 ,  H01L21/28264 ,  H01L21/28587 ,  H01L29/42316 ,  H01L29/42376 ,  H01L29/517 ,  H01L29/66462 ,  H01L29/66871 ,  H01L29/78 ,  Y10S430/143 ,  Y10S438/949 ,  Y10S438/95 ,  Y10S438/951

Abstract: A semiconductor device has: a semiconductor substrate having a pair of current input/output regions via which current flows; an insulating film formed on the semiconductor substrate and having a gate electrode opening; and a mushroom gate electrode structure formed on the semiconductor substrate via the gate electrode opening, the mushroom gate electrode structure having a stem and a head formed on the stem, the stem having a limited size on the semiconductor substrate along a current direction and having a forward taper shape upwardly and monotonically increasing the size along the current direction, the head having a size expanded stepwise along the current direction, and the stem contacting the semiconductor substrate in the gate electrode opening and riding the insulating film near at a position of at least one of opposite ends of the stem along the current direction.

Abstract translation: 半导体器件具有：半导体衬底，具有电流流过的一对电流输入/输出区域; 形成在所述半导体基板上并具有栅电极开口的绝缘膜; 以及通过所述栅电极开口形成在所述半导体基板上的蘑菇栅极电极结构，所述蘑菇栅电极结构具有杆和形成在所述杆上的头部，所述杆在所述半导体衬底上沿着电流方向具有有限的尺寸，并且具有 向前锥形形状向上并沿着电流方向单调地增加尺寸，头部具有沿着电流方向逐步扩大的尺寸，并且杆在栅极电极开口中接触半导体衬底并且在至少一个位置附近骑绝缘膜 杆的相对端之一沿着当前方向。

公开(公告)号：US20070161220A1

公开(公告)日：2007-07-12

申请号：US11713599

申请日：2007-03-05

Applicant: Kozo Makiyama ,  Naoya Ikechi ,  Takahiro Tan

Inventor： Kozo Makiyama ,  Naoya Ikechi ,  Takahiro Tan

IPC: H01L21/3205

CPC classification number: H01L21/0274 ,  H01L21/28114 ,  H01L21/28264 ,  H01L21/28587 ,  H01L29/42316 ,  H01L29/42376 ,  H01L29/517 ,  H01L29/66462 ,  H01L29/66871 ,  H01L29/78 ,  Y10S430/143 ,  Y10S438/949 ,  Y10S438/95 ,  Y10S438/951

Abstract: A semiconductor device has: a semiconductor substrate having a pair of current input/output regions via which current flows; an insulating film formed on the semiconductor substrate and having a gate electrode opening; and a mushroom gate electrode structure formed on the semiconductor substrate via the gate electrode opening, the mushroom gate electrode structure having a stem and a head formed on the stem, the stem having a limited size on the semiconductor substrate along a current direction and having a forward taper shape upwardly and monotonically increasing the size along the current direction, the head having a size expanded stepwise along the current direction, and the stem contacting the semiconductor substrate in the gate electrode opening and riding the insulating film near at a position of at least one of opposite ends of the stem along the current direction.

公开(公告)号：US20060220165A1

公开(公告)日：2006-10-05

申请号：US10519877

申请日：2003-07-15

Applicant: Ichiro Hase

Inventor： Ichiro Hase

IPC: H01L31/07

CPC classification number: H01L29/66462 ,  H01L21/28587 ,  H01L29/7785

Abstract: There is provided a semiconductor device capable of ensuring a complete enhancement-mode operation and realizing a power transistor excellent in the low-distortion, high-efficiency performance. On a surface of a substrate (1) composed of single crystal GaAs, a second barrier layer (3) composed of AlGaAs, a channel layer (4) composed of InGaAs, a third barrier layer (12) composed of InGaP and a first barrier layer (11) composed of AlGaAs are stacked in this order, while placing in between a buffer layer (2). Relation of χ1−χ3≦0.5*(Eg3-Eg1), where χ1 is electron affinity of the first barrier layer (11), Eg1 is a band gap of the same, χ3 is electron affinity of the third barrier layer (12), and Eg3 is a band gap of the same, is satisfied between the first barrier layer (11) and the third barrier layer (12).

Abstract translation: 提供了能够确保完全增强模式操作并实现低失真，高效率性能优异的功率晶体管的半导体器件。 在由单晶GaAs构成的基板（1）的表面上，由AlGaAs构成的第二势垒层（3），由InGaAs构成的沟道层（4），由InGaP构成的第三势垒层（12） 依次层叠由AlGaAs构成的层（11），同时放置在缓冲层（2）之间。 i chi chi chi chi chi chi chi chi chi chi chi chi chi where <<<<<< 1是第一阻挡层（11）的电子亲和力，Eg 1是与之相同的带隙，chi 3是电子亲和力 在第一阻挡层（11）和第三阻挡层（12）之间，满足第三阻挡层（12）和第三阻挡层（12）和其间的带隙。

公开(公告)号：US07071088B2

公开(公告)日：2006-07-04

申请号：US10227105

申请日：2002-08-23

Applicant: Michael P. C. Watts ,  Sidlgata V. Sreenivasan

Inventor： Michael P. C. Watts ,  Sidlgata V. Sreenivasan

IPC: H01L21/44

CPC classification number: G03F7/0002 ,  B82Y10/00 ,  B82Y40/00 ,  H01L21/0272 ,  H01L21/28587 ,  H01L21/312 ,  H01L21/76804 ,  H01L21/76817

Abstract: The present invention provides a method for fabricating bulbous-shaped vias on a substrate, having a surface, by disposing, on the substrate, a polymerizable fluid composition. A mold is placed in contact with the polymerizable fluid composition. The mold includes a relief structure on a surface thereof to create a recess in a layer of the polymerizable fluid composition. The polymerizable fluid composition is subjected to conditions to cause polymerization, forming a polymerized layer having a solidified indentation. An opening to the surface of the substrate is formed by removing material disposed on the substrate surface through etch processes. In a further embodiment a conductive layer may be disposed in the opening to form a gate. A lift-off process may be employed to remove the polymerized layer.

Abstract translation: 本发明提供一种在基板上制造球状通孔的方法，其具有通过在基板上设置可聚合流体组合物的表面。 将模具放置成与可聚合流体组合物接触。 模具在其表面上包括浮雕结构，以在可聚合流体组合物的层中形成凹部。 可聚合流体组合物经历引起聚合的条件，形成具有固化压痕的聚合层。 通过蚀刻处理去除设置在基板表面上的材料来形成通向基板表面的开口。 在另一个实施例中，导电层可以设置在开口中以形成栅极。 可以采用剥离工艺来除去聚合层。

公开(公告)号：US20050145851A1

公开(公告)日：2005-07-07

申请号：US10879695

申请日：2004-06-28

Applicant: Jerry Johnson ,  Ricardo Borges ,  Jeffrey Brown ,  James Cook ,  Allen Hanson ,  Edwin Piner ,  Pradeep Rajagopal ,  John Roberts ,  Sameer Singhal ,  Robert Therrien ,  Andrei Vescan

Inventor： Jerry Johnson ,  Ricardo Borges ,  Jeffrey Brown ,  James Cook ,  Allen Hanson ,  Edwin Piner ,  Pradeep Rajagopal ,  John Roberts ,  Sameer Singhal ,  Robert Therrien ,  Andrei Vescan

IPC: H01L21/285 ,  H01L21/329 ,  H01L21/335 ,  H01L29/20 ,  H01L29/872 ,  H01L29/15

CPC classification number: H01L29/7787 ,  H01L21/28587 ,  H01L21/7605 ,  H01L29/2003 ,  H01L29/66212 ,  H01L29/66462 ,  H01L29/872

Abstract: Gallium nitride material structures, including devices, and methods associated with the same are provided. In some embodiments, the structures include one or more isolation regions which electrically isolate adjacent devices. One aspect of the invention is the discovery that the isolation regions also can significantly reduce the leakage current of devices (e.g., transistors) made from the structures, particularly devices that also include a passivating layer formed on a surface of the gallium nitride material. Lower leakage currents can result in increased power densities and operating voltages, amongst other advantages.

Abstract translation: 提供了氮化镓材料结构，包括器件和与其相关的方法。 在一些实施例中，结构包括一个或多个隔离相邻器件的隔离区域。 本发明的一个方面是发现隔离区域还可以显着地减少由结构制成的器件（例如，晶体管）的泄漏电流，特别是还包括形成在氮化镓材料表面上的钝化层的器件。 较低的漏电流可以导致增加的功率密度和工作电压以及其它优点。

公开(公告)号：US20050133818A1

公开(公告)日：2005-06-23

申请号：US10740376

申请日：2003-12-17

Applicant: Jerry Johnson ,  Robert Therrien ,  Andrei Vescan ,  Jeffrey Brown

Inventor： Jerry Johnson ,  Robert Therrien ,  Andrei Vescan ,  Jeffrey Brown

IPC: H01L21/285 ,  H01L21/329 ,  H01L21/335 ,  H01L29/20 ,  H01L29/872 ,  H01L31/0328

CPC classification number: H01L29/66212 ,  H01L21/28587 ,  H01L29/2003 ,  H01L29/66462 ,  H01L29/872

Abstract: Gallium nitride material devices and methods of forming the same are provided. The devices include an electrode-defining layer. The electrode-defining layer typically has a via formed therein in which an electrode is formed (at least in part). Thus, the via defines (at least in part) dimensions of the electrode. In some cases, the electrode-defining layer is a passivating layer that is formed on a gallium nitride material region.

Abstract translation: 提供了氮化镓材料器件及其形成方法。 这些装置包括电极限定层。 电极限定层通常形成有在其中形成电极（至少部分）的通孔。 因此，通孔限定（至少部分地）电极的尺寸。 在一些情况下，电极限定层是形成在氮化镓材料区域上的钝化层。

公开(公告)号：US20050127398A1

公开(公告)日：2005-06-16

申请号：US11038255

申请日：2005-01-21

Applicant: Satoshi Taniguchi ,  Toshikazu Suzuki ,  Hideki Ono ,  Jun Araseki

Inventor： Satoshi Taniguchi ,  Toshikazu Suzuki ,  Hideki Ono ,  Jun Araseki

IPC: H01L21/28 ,  H01L21/285 ,  H01L21/302 ,  H01L21/3065 ,  H01L21/335 ,  H01L21/338 ,  H01L21/8234 ,  H01L29/20 ,  H01L29/423 ,  H01L29/47 ,  H01L29/778 ,  H01L29/812 ,  H01L29/872 ,  H01L31/0328 ,  H01L31/072

CPC classification number: H01L29/66462 ,  H01L21/28587 ,  H01L29/2003 ,  H01L29/42316 ,  H01L29/7787

Abstract: A method for making a filed-effect semiconductor device includes the steps of forming a gate electrode on a semiconductor layer composed of a gallium nitride-based compound semiconductor represented by the formula AlxInyGa1−x−yN, wherein x+y=1, 0≦x≦1, and 0≦y≦1; and forming a source electrode and a drain electrode by self-alignment using the gate electrode as a mask. A field-effect semiconductor device fabricated by the method is also disclosed.

Abstract translation: 一种场效应半导体器件的制造方法包括以下步骤：在由式Al x Y y表示的基于氮化镓的化合物半导体构成的半导体层上形成栅电极， 其中x + y = 1,0 <= x <= 1，0 <= y <= 1; 并且使用栅电极作为掩模，通过自对准形成源电极和漏电极。 还公开了通过该方法制造的场效应半导体器件。

公开(公告)号：US06835635B2

公开(公告)日：2004-12-28

申请号：US10316210

申请日：2002-12-10

Applicant: Hiroyuki Seto ,  Makoto Inai ,  Hiroyuki Nakano ,  Eiji Tai

Inventor： Hiroyuki Seto ,  Makoto Inai ,  Hiroyuki Nakano ,  Eiji Tai

IPC: H01L2128

CPC classification number: H01L29/66863 ,  H01L21/0272 ,  H01L21/28587

Abstract: A gate electrode is formed in the following manner. A first resist layer having a first opening is formed on a semiconductor substrate. A second resist layer having a second opening larger than the first opening is formed on the first resist layer. A first conductor layer containing a high-melting-point metal is formed. Subsequently, a second conductor layer containing low-resistance metal is formed, and then the first conductor layer within the second opening is removed by etching. Next, the second resist layer is removed by a lift-off process, and finally the first resist layer is removed by ashing.

Abstract translation: 以下列方式形成栅电极。 在半导体衬底上形成具有第一开口的第一抗蚀剂层。 在第一抗蚀剂层上形成具有大于第一开口的第二开口的第二抗蚀剂层。 形成含有高熔点金属的第一导体层。 随后，形成含有低电阻金属的第二导体层，然后通过蚀刻去除第二开口内的第一导体层。 接下来，通过剥离处理去除第二抗蚀剂层，最后通过灰化除去第一抗蚀剂层。

公开(公告)号：US06797994B1

公开(公告)日：2004-09-28

申请号：US09504660

申请日：2000-02-14

Applicant: William E. Hoke ,  Katerina Y. Hur

Inventor： William E. Hoke ,  Katerina Y. Hur

IPC: H01L310328

CPC classification number: H01L29/66462 ,  H01L21/28587 ,  H01L29/7785

Abstract: A transistor structure is provided. This structure has a source electrode and a drain electrode. A doped cap layer of GaxIn1−xAs is disposed below the source electrode and the drain electrode and provides a cap layer opening. An undoped resistive layer of GaxIn1−xAs is disposed below the cap layer and defines a resistive layer opening in registration with the cap layer opening and having a first width. A Schottky layer of AlyIn1−yAs is disposed below the resistive layer. An undoped channel layer is disposed below the Schottky layer. A semi-insulating substrate is disposed below the channel layer. A top surface of the Schottky layer beneath the resistive layer opening provides a recess having a second width smaller than the first width. A gate electrode is in contact with a bottom surface of the recess provided by the Schottky layer.

Abstract translation: 提供晶体管结构。 该结构具有源极和漏极。 GaxIn1-xAs的掺杂覆盖层设置在源电极和漏电极下方并提供盖层开口。 GaxIn1-xAs的未掺杂电阻层设置在盖层下方并且限定与盖层开口对准的电阻层，并具有第一宽度。 AlyIn1-yAs的肖特基层设置在电阻层下方。 未掺杂沟道层设置在肖特基层下方。 半绝缘基板设置在沟道层下方。 电阻层开口下方的肖特基层的顶表面提供具有小于第一宽度的第二宽度的凹部。 栅电极与由肖特基层提供的凹部的底表面接触。