公开(公告)号：US20120294088A1

公开(公告)日：2012-11-22

申请号：US13564883

申请日：2012-08-02

Applicant: Tomoharu Tanaka

Inventor： Tomoharu Tanaka

IPC: G11C16/04

CPC classification number: G06F12/0893 ,  G06F2212/2022 ,  G11C16/0483 ,  G11C16/10 ,  G11C2207/2245 ,  G11C2216/14

Abstract: Bit lines of a memory segment are read at substantially the same time by coupling a selected memory segment and, at some of the data lines of any intervening segments, to respective data caches. The bit lines of the unselected memory segments that are not used to couple the selected segment to the data caches can be coupled to their respective source lines.

Abstract translation: 通过将所选择的存储器段和任何中间段的某些数据线耦合到相应的数据高速缓冲存储器，基本上同时读取存储器段的位线。 不用于将所选择的段耦合到数据高速缓存的未选择的存储器段的位线可以耦合到它们各自的源极线。

公开(公告)号：US08289780B2

公开(公告)日：2012-10-16

申请号：US12792071

申请日：2010-06-02

Applicant: Sung-Won Yun ,  Oh-suk Kwon

Inventor： Sung-Won Yun ,  Oh-suk Kwon

IPC: G11C16/06

CPC classification number: G11C11/5628 ,  G11C16/3459 ,  G11C2211/5621 ,  G11C2216/14

Abstract: A page buffer includes a sense latch, a data latch and a page buffer controller. The sense latch is connected to a bit line, and is configured to set stored data in response to a sense latch control signal, and to change the stored data in response to a signal applied to the bit line in a data verification operation. The data latch is configured to store multi-bit data to be programmed in a program operation, and to set stored data in response to a data latch control signal in the data verification operation. The page buffer controller is configured to control the bit line in accordance with the multi-bit data stored in the data latch in the program operation, and to output the sense latch control signal and the data latch control signal in accordance with the multi-bit data stored in the data latch in response to a control signal in the data verification operation.

Abstract translation: 页面缓冲器包括检测锁存器，数据锁存器和页面缓冲器控制器。 感测锁存器连接到位线，并且被配置为响应于感测锁存控制信号设置存储的数据，并且响应于在数据验证操作中施加到位线的信号来改变存储的数据。 数据锁存器被配置为存储要在编程操作中编程的多位数据，并且在数据验证操作中响应于数据锁存控制信号来设置存储的数据。 页缓冲器控制器被配置为在编程操作中根据存储在数据锁存器中的多位数据来控制位线，并且根据多位输出读出锁存控制信号和数据锁存控制信号 响应于数据验证操作中的控制信号而存储在数据锁存器中的数据。

公开(公告)号：US08279668B2

公开(公告)日：2012-10-02

申请号：US12801532

申请日：2010-06-14

Applicant: Kyoung Lae Cho ,  Yoon Dong Park ,  Jun Jin Kong ,  Jong Han Kim ,  Jae Hong Kim ,  Young Hwan Lee ,  Heeseok Eun ,  Seung-Hwan Song

Inventor： Kyoung Lae Cho ,  Yoon Dong Park ,  Jun Jin Kong ,  Jong Han Kim ,  Jae Hong Kim ,  Young Hwan Lee ,  Heeseok Eun ,  Seung-Hwan Song

IPC: G11C16/04

CPC classification number: G11C11/5628 ,  G11C29/00 ,  G11C2216/14

Abstract: A memory programming apparatuses and/or methods are provided. The memory programming apparatus may include a data storage unit, a first counting unit, an index storage unit and/or a programming unit. The data storage unit may be configured to store a data page. The first counting unit may be configured to generate index information by counting a number of cells included in at least one reference threshold voltage state based on the data page. The index storage unit may be configured to store, the generated index information. The programming unit may be configured to store the data page in the data storage unit and store the generated index information in the index storage unit. The first counting unit may send the generated index information to the programming unit. The memory programming apparatus can monitor distribution states of threshold voltages in memory cells.

Abstract translation: 提供了存储器编程设备和/或方法。 存储器编程装置可以包括数据存储单元，第一计数单元，索引存储单元和/或编程单元。 数据存储单元可以被配置为存储数据页。 第一计数单元可以被配置为通过基于数据页计数包括在至少一个参考阈值电压状态中的单元的数量来生成索引信息。 索引存储单元可以被配置为存储所生成的索引信息。 编程单元可以被配置为将数据页存储在数据存储单元中，并将生成的索引信息存储在索引存储单元中。 第一计数单元可以将生成的索引信息发送到编程单元。 存储器编程装置可以监视存储器单元中阈值电压的分布状态。

公开(公告)号：US20120206980A1

公开(公告)日：2012-08-16

申请号：US13455018

申请日：2012-04-24

Applicant: ROBERT NORMAN

Inventor： ROBERT NORMAN

IPC: G11C7/10

CPC classification number: G11C7/1096 ,  G11C5/02 ,  G11C7/1006 ,  G11C7/1078 ,  G11C7/1087 ,  G11C8/10 ,  G11C13/0033 ,  G11C13/004 ,  G11C13/0064 ,  G11C13/0069 ,  G11C16/10 ,  G11C16/26 ,  G11C16/3427 ,  G11C2013/0085 ,  G11C2013/0088 ,  G11C2213/71 ,  G11C2216/14

Abstract: Embodiments of the invention relate generally to data storage and computer memory, and more particularly, to systems, integrated circuits and methods for accessing memory in multiple layers of memory implementing, for example, third dimension memory technology. In a specific embodiment, an integrated circuit is configured to implement write buffers to access multiple layers of memory. For example, the integrated circuit can include memory cells disposed in multiple layers of memory. In one embodiment, the memory cells can be third dimension memory cells. The integrated circuit can also include read buffers that can be sized differently than the write buffers. In at least one embodiment, write buffers can be sized as a function of a write cycle. Each layer of memory can include a plurality of two-terminal memory elements that retain stored data in the absence of power and store data as a plurality of conductivity profiles.

Abstract translation: 本发明的实施例一般涉及数据存储和计算机存储器，更具体地，涉及用于访问实现例如第三维存储器技术的多层存储器中的存储器的系统，集成电路和方法。 在具体实施例中，集成电路被配置为实现写入缓冲器以访问多层存储器。 例如，集成电路可以包括设置在多层存储器中的存储单元。 在一个实施例中，存储器单元可以是第三维存储器单元。 集成电路还可以包括可以与写入缓冲器不同的读取缓冲器。 在至少一个实施例中，写入缓冲器的大小可以作为写周期的函数。 每层存储器可以包括多个两端存储元件，其在不存在功率的情况下保存存储的数据，并将数据存储为多个导电率分布。

公开(公告)号：US08223547B2

公开(公告)日：2012-07-17

申请号：US13027055

申请日：2011-02-14

Applicant: Kevin M. Conley ,  John S. Mangan ,  Jeffrey G. Craig

Inventor： Kevin M. Conley ,  John S. Mangan ,  Jeffrey G. Craig

IPC: G11C16/04

CPC classification number: G11C16/107 ,  G06F12/0246 ,  G06F2212/7203 ,  G06F2212/7207 ,  G06F2212/7208 ,  G11C16/10 ,  G11C16/3459 ,  G11C29/82 ,  G11C2216/14

Abstract: A non-volatile memory system is formed of floating gate memory cells arranged in blocks as the smallest unit of memory cells that are erasable together. The system includes a number of features that may be implemented individually or in various cooperative combinations. One feature is the storage in separate blocks of the characteristics of a large number of blocks of cells in which user data is stored. These characteristics for user data blocks being accessed may, during operation of the memory system by its controller, be stored in a random access memory for ease of access and updating. According to another feature, multiple sectors of user data are stored at one time by alternately streaming chunks of data from the sectors to multiple memory blocks. Bytes of data in the stream may be shifted to avoid defective locations in the memory such as bad columns. Error correction codes may also be generated from the streaming data with a single generation circuit for the multiple sectors of data. The stream of data may further be transformed in order to tend to even out the wear among the blocks of memory. Yet another feature, for memory systems having multiple memory integrated circuit chips, provides a single system record that includes the capacity of each of the chips and assigned contiguous logical address ranges of user data blocks within the chips which the memory controller accesses when addressing a block, making it easier to manufacture a memory system with memory chips having different capacities. A typical form of the memory system is as a card that is removably connectable with a host system but may alternatively be implemented in a memory embedded in a host system. The memory cells may be operated with multiple states in order to store more than one bit of data per cell.

Abstract translation: 非易失性存储器系统由以块为单位布置的浮动栅极存储单元形成为可以一起可擦除的最小单元的存储器单元。 该系统包括可以单独地或以各种协作组合实现的多个特征。 一个特征是在单独的块中存储其中存储用户数据的大量小区块的特性。 正在访问的用户数据块的这些特征可以在存储器系统由其控制器操作期间被存储在随机存取存储器中以便于访问和更新。 根据另一特征，通过将来自扇区的数据块交替地流向多个存储块，一次存储多个扇区的用户数据。 可以移动流中的数据字节以避免存储器中的不良位置，例如不良列。 也可以通过用于多扇区数据的单一生成电路从流数据生成纠错码。 可以进一步转换数据流，以便趋向于均匀地消除存储器块之间的磨损。 对于具有多个存储器集成电路芯片的存储器系统，又一特征提供了单个系统记录，该系统记录包括每个芯片的容量，并且在寻址块时存储器控制器访问的芯片内分配的用户数据块的连续逻辑地址范围 ，使得容易制造具有不同容量的存储器芯片的存储器系统。 存储器系统的典型形式是可拆卸地与主机系统连接的卡，但是也可以在嵌入在主机系统中的存储器中实现。 存储器单元可以以多种状态操作，以便存储每个单元的多于一位的数据。

公开(公告)号：US08218373B2

公开(公告)日：2012-07-10

申请号：US12981063

申请日：2010-12-29

Applicant: Hiroshi Nakamura ,  Kenichi Imamiya ,  Toshio Yamamura ,  Koji Hosono ,  Koichi Kawai

Inventor： Hiroshi Nakamura ,  Kenichi Imamiya ,  Toshio Yamamura ,  Koji Hosono ,  Koichi Kawai

IPC: G11C7/10

CPC classification number: G11C16/3459 ,  G06F3/0659 ,  G06F12/0246 ,  G11C7/065 ,  G11C7/1006 ,  G11C7/1051 ,  G11C7/106 ,  G11C7/1063 ,  G11C16/06 ,  G11C16/08 ,  G11C16/10 ,  G11C16/26 ,  G11C2207/104 ,  G11C2216/14

Abstract: In a semiconductor integrated circuit, an internal circuit is capable of executing a first operation and a second operation concurrently, and an output circuit outputs to the outside of the semiconductor integrated circuit information indicating whether or not the first operation is being executed and information indicating whether or not the second operation is executable.

Abstract translation: 在半导体集成电路中，内部电路能够同时执行第一操作和第二操作，并且输出电路向半导体集成电路的外部输出指示是否正在执行第一操作的信息以及指示是否 或者不是第二操作是可执行的。

公开(公告)号：US20120140572A1

公开(公告)日：2012-06-07

申请号：US13181800

申请日：2011-07-13

Applicant: Jae Yun KIM ,  Young Soo PARK ,  Eui Sang YOON

Inventor： Jae Yun KIM ,  Young Soo PARK ,  Eui Sang YOON

IPC: G11C7/10

CPC classification number: G11C16/30 ,  G11C2207/2227 ,  G11C2216/14

Abstract: A semiconductor memory device includes a switching element coupled between a power supply line and an output terminal of a power supply circuit for supplying a power supply voltage, wherein the switching element is configured to be turned on in response to a standby signal, a page buffer including a plurality of latch circuits, wherein a voltage input terminal of at least one of the latch circuits is coupled to the output terminal of the power supply circuit and a voltage input terminal of at least another one of the latch circuits is coupled to the power supply line, and a control logic circuit configured to generate the standby signal according to an operation mode of the semiconductor memory device.

Abstract translation: 一种半导体存储器件，包括一个开关元件，该开关元件连接在供电线路和用于提供电源电压的电源电路的输出端子之间，其中该开关元件被配置为响应待机信号导通，一个页面缓冲器 包括多个锁存电路，其中至少一个锁存电路的电压输入端耦合到电源电路的输出端，并且至少另一个锁存电路的电压输入端耦合到电源 电源线，以及控制逻辑电路，被配置为根据半导体存储器件的操作模式产生待机信号。

公开(公告)号：US20120113722A1

公开(公告)日：2012-05-10

申请号：US13285697

申请日：2011-10-31

Applicant: Seiichi Aritome

Inventor： Seiichi Aritome

IPC: G11C16/10

CPC classification number: G11C16/12 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/0491 ,  G11C16/3418 ,  G11C16/3427 ,  G11C16/3459 ,  G11C2211/5621 ,  G11C2211/5642 ,  G11C2216/14

Abstract: Memory devices and methods of programming memory cells including selecting a voltage to apply to a control gate of the memory cell during programming of a data value of a sense amplifier to the memory cell in response to at least a data value contained in a data latch that is in communication with the sense amplifier.

Abstract translation: 存储器装置和编程存储器单元的方法，包括响应于包含在数据锁存器中的至少一个数据值，在将读出放大器的数据值编程到存储器单元期间选择施加到存储器单元的控制栅极的电压， 与感应放大器通信。

公开(公告)号：US20120113715A1

公开(公告)日：2012-05-10

申请号：US13285698

申请日：2011-10-31

Applicant: Raul-Adrian Cernea

Inventor： Raul-Adrian Cernea

IPC: G11C16/26 ,  G11C16/04 ,  G11C16/06

CPC classification number: G11C7/062 ,  G11C7/04 ,  G11C7/067 ,  G11C7/08 ,  G11C7/22 ,  G11C7/227 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/10 ,  G11C16/26 ,  G11C16/28 ,  G11C2211/5621 ,  G11C2216/14 ,  G11C2216/22

Abstract: One or more sense amplifiers for sensing the conduction current of non-volatile memory is controlled by signals that are timed by a reference sense amplifier having similar characteristics and operating conditions. In one aspect, a sensing period is determined by when the reference sense amplifier sensing a reference current detects an expected state. In another aspect, an integration period for an amplified output is determined by when the reference sense amplifier outputs an expected state. When these determined timings are used to control the one or more sense amplifiers, environment and systemic variations are tracked.

Abstract translation: 用于感测非易失性存储器的传导电流的一个或多个感测放大器由具有相似特性和操作条件的参考读出放大器定时的信号控制。 在一个方面，感测周期由感测参考电流的参考读出放大器何时检测到预期状态来确定。 在另一方面，放大输出的积分周期由参考读出放大器何时输出预期状态来确定。 当这些确定的定时用于控制一个或多个感测放大器时，跟踪环境和系统变化。

公开(公告)号：US20120099387A1

公开(公告)日：2012-04-26

申请号：US13280421

申请日：2011-10-25

Applicant: Sunil Shim ,  Woonkyung Lee ,  Jaehoon Jang ,  Kihyun Kim

Inventor： Sunil Shim ,  Woonkyung Lee ,  Jaehoon Jang ,  Kihyun Kim

IPC: G11C7/10 ,  G11C7/12

CPC classification number: G11C7/12 ,  G11C16/0483 ,  G11C16/24 ,  G11C16/26 ,  G11C2216/14 ,  H01L27/0688 ,  H01L27/11582 ,  H01L29/7926

Abstract: A nonvolatile memory device includes a substrate, multiple doping regions, multiple cell strings and multiple page buffers. The doping regions extend in a first direction along the substrate and are spaced apart from one another in a second direction. The cell strings are provided according to a specific pattern between adjacent first and second doping regions among the multiple regions, each of the cell strings including multiple cell transistors stacked in a third direction perpendicular to the substrate. The page buffers are connected to the cell strings through bit lines, the page buffers being configured to provide precharge voltages to the bit lines during a read operation. Levels of the precharge voltages provided to the bit lines vary depending on distances between the cell strings and at least one of the first and second doping regions, respectively.

Abstract translation: 非易失性存储器件包括衬底，多个掺杂区域，多个单元串和多页缓冲器。 掺杂区域沿着衬底在第一方向上延伸并且在第二方向上彼此间隔开。 根据多个区域中的相邻的第一和第二掺杂区域之间的特定图案提供单元串，每个单元串包括在与基板垂直的第三方向上堆叠的多个单元晶体管。 页缓冲器通过位线连接到单元串，页缓冲器被配置为在读操作期间向位线提供预充电电压。 提供给位线的预充电电压的电平分别根据电池串与第一和第二掺杂区域中的至少一个之间的距离而变化。