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公开(公告)号：US09337886B1
公开(公告)日：2016-05-10
申请号：US14137177
申请日：2013-12-20
Applicant: Xilinx, Inc.
Inventor： Christopher H. Dick
CPC classification number: H04B1/0475 , H03F1/3241 , H04B2001/0425
Abstract: A system for digital pre-distortion includes: a transmitter configured to transmit at least one transmission data signal; a receiver configured to receive at least one receive data signal and to receive the at least one transmission data signal; and at least one amplifier, associated with the transmitter, configured to receive at least one pre-distortion control signal sent from the receiver; wherein the at least one pre-distortion control signal is related to the at least one transmission data signal.
Abstract translation: 一种用于数字预失真的系统包括：被配置为发送至少一个传输数据信号的发射机; 接收器，被配置为接收至少一个接收数据信号并接收所述至少一个传输数据信号; 以及与所述发射机相关联的至少一个放大器，被配置为接收从所述接收机发送的至少一个预失真控制信号; 其中所述至少一个预失真控制信号与所述至少一个传输数据信号有关。
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公开(公告)号：US11573726B1
公开(公告)日：2023-02-07
申请号：US17097917
申请日：2020-11-13
Applicant: Xilinx, Inc.
Inventor： Juan J. Noguera Serra , Goran H K Bilski , Jan Langer , Baris Ozgul , Richard L. Walke , Ralph D. Wittig , Kornelis A. Vissers , Christopher H. Dick , Philip B. James-Roxby
IPC: G06F3/06 , G06F15/173 , G06F15/78
Abstract: A device may include a plurality of data processing engines. Each of the data processing engines may include a memory pool having a plurality of memory banks, a plurality of cores each coupled to the memory pool and configured to access the plurality of memory banks, a memory mapped switch coupled to the memory pool and a memory mapped switch of at least one neighboring data processing engine, and a stream switch coupled to each of the plurality of cores and to a stream switch of the at least one neighboring data processing engine.
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公开(公告)号：US10990552B1
公开(公告)日：2021-04-27
申请号：US15944464
申请日：2018-04-03
Applicant: Xilinx, Inc.
Inventor： Goran Hk Bilski , Peter McColgan , Juan J. Noguera Serra , Baris Ozgul , Jan Langer , Richard L. Walke , Ralph D. Wittig , Kornelis A. Vissers , Philip B. James-Roxby , Christopher H. Dick
Abstract: Examples herein describe techniques for communicating between data processing engines in an array of data processing engines. In one embodiment, the array is a 2D array where each of the DPEs includes one or more cores. In addition to the cores, the data processing engines can include a memory module (with memory banks for storing data) and an interconnect which provides connectivity between the engines. To transmit processed data, a data processing engine identifies a destination processing engine in the array. Once identified, the data processing engine can transmit the processed data using a reserved point-to-point communication path in the interconnect that couples the source and destination data processing engines.
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公开(公告)号：US10747502B2
公开(公告)日：2020-08-18
申请号：US16136041
申请日：2018-09-19
Applicant: Xilinx, Inc.
Inventor： Satyaprakash Pareek , Anup Hosangadi , Bing Tian , Ashish Sirasao , Yao Fu , Oscar Fernando C. Fernandez , Michael Wu , Christopher H. Dick
Abstract: Circuits and method for multiplying floating point operands. An exponent adder circuit sums a first exponent and a second exponent and generates an output exponent. A mantissa multiplier circuit multiplies a first mantissa and a second mantissa and generates an output mantissa. A first conversion circuit converts the output exponent and output mantissa into a fixed point number. An accumulator circuit sums contents of an accumulation register and the fixed point number into an accumulated value and stores the accumulated value in the accumulation register.
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35.发明授权公开(公告)号：US09973363B1
公开(公告)日：2018-05-15
申请号：US15160998
申请日：2016-05-20
Applicant: Xilinx, Inc.
Inventor： Nihat E. Tunali , Michael Wu , Christopher H. Dick
IPC: H04L27/01 , H04L27/26 , H04J4/00 , H04J1/04 , H04B7/0491
CPC classification number: H04L27/2627 , H04B7/0491 , H04J1/045 , H04J4/005 , H04L27/01 , H04L27/2647 , H04L27/265
Abstract: A method includes receiving frequency domain (FD) symbols associated with data symbols transmitted in a channel on a frame including a plurality of subcarriers and a plurality of time-slots. An equalization process is performed to the received FD symbols to generate FD equalized symbols. The FD equalized symbols is transformed to time domain (TD) symbols. A demodulation process is performed to the TD symbols to provide estimates of the data symbols.
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Patent Agency Ranking
公开(公告)号：US09935810B1
公开(公告)日：2018-04-03
申请号：US15451933
申请日：2017-03-07
Applicant: Xilinx, Inc.
Inventor： Nikolaus H. Hammler , Christopher H. Dick
CPC classification number: H04L27/367 , H03F1/3247 , H03F1/3258 , H03F3/195 , H03M1/12 , H03M1/66 , H04L25/0242 , H04L25/025
Abstract: A model identification system includes an analog to digital converter (ADC). The ADC includes a conversion circuit configured to receive a first analog signal and generate a first digital signal including samples having a first rate by sampling the first analog signal at the first rate. The ADC further includes a first digital signal processing (DSP) circuit configured to generate a second digital signal including samples having a second rate less than the first rate based on the second digital signal and a first sampling matrix. The first sampling matrix is a block diagonal matrix including a plurality of diagonal blocks, each diagonal block is a row vector including a plurality of elements.
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公开(公告)号：US09727416B2
公开(公告)日：2017-08-08
申请号：US14789017
申请日：2015-07-01
Applicant: Xilinx, Inc.
Inventor： Christopher H. Dick
CPC classification number: G06F11/1068 , G06F11/1008 , G06F11/1012 , G06F11/1072 , G11C29/52 , H03M13/1102 , H03M13/1111 , H03M13/353 , H03M13/635 , H03M13/6393
Abstract: An apparatus, as well as a method therefor, relates generally to managing reliability of a solid state storage. In such an apparatus, there is a memory controller for providing a code rate. An encoder is for receiving input data and the code rate for providing encoded data. The solid-state storage is for receiving and storing the encoded data. A decoder is for accessing the encoded data stored in the solid-state storage and for receiving the code rate for providing decoded data of the encoded data accessed. The decoded data is provided as soft decisions representing probabilities of the decoded data. The memory controller is for receiving the decoded data for adjusting the code rate responsive to the probabilities of the decoded data.
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公开(公告)号：US20170012598A1
公开(公告)日：2017-01-12
申请号：US14791852
申请日：2015-07-06
Applicant: Xilinx, Inc.
Inventor： Fredric J. Harris , Christopher H. Dick
IPC: H03H7/12
CPC classification number: H03H7/12 , H03H17/0266
Abstract: An apparatus, and related method, relates generally to viable bandwidth filtering. In such an apparatus, an analysis filter bank has path filters associated with different bandwidths and is configured for filtering and transforming an input signal having a first bandwidth into a first interleaved output. A mask is coupled to the analysis filter bank and configured for masking at least one narrowband time signal of the first interleaved output. A synthesis filter bank is coupled to the mask. The synthesis filter bank is configured for transforming and filtering the masked first interleaved output to generate a second interleaved output for constructing an output signal having a second bandwidth. The second bandwidth is different than the first bandwidth for the variable bandwidth filtering.
Abstract translation: 一种装置和相关方法一般涉及可行的带宽过滤。 在这种装置中，分析滤波器组具有与不同带宽相关联的路径滤波器，并且被配置用于将具有第一带宽的输入信号滤波和变换为第一交错输出。 掩模耦合到分析滤波器组并且被配置用于掩蔽第一交错输出的至少一个窄带时间信号。 合成滤波器组耦合到掩模。 合成滤波器组被配置用于对被屏蔽的第一交错输出进行变换和滤波，以产生用于构造具有第二带宽的输出信号的第二交错输出。 第二个带宽与可变带宽过滤的第一个带宽不同。
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39.发明申请M-PATH FILTER WITH OUTER AND INNER CHANNELIZERS FOR PASSBAND BANDWIDTH ADJUSTMENT 有权M-PATH过滤器，带外部和内部通道，用于通带宽度调整公开(公告)号：US20170012596A1
公开(公告)日：2017-01-12
申请号：US14791811
申请日：2015-07-06
Applicant: Xilinx, Inc.
Inventor： Fredric J. Harris , Christopher H. Dick
IPC: H03H7/01
CPC classification number: H03H17/0266
Abstract: Disclosed is apparatus and method to filter a signal. In such an apparatus, an outer polyphase filter is configured for receiving an input signal and for channelizing the input signal into outer filtered samples. An outer Inverse Fourier Transform block is coupled to the outer polyphase filter and configured for transforming the outer filtered samples into a coarse multi-path output. An inner polyphase filter is coupled to a path of the coarse multi-path output for receiving information therefrom and configured for generating inner filtered samples of the information obtained from the path. The inner filtered samples are for moving an edge of a passband associated with the outer filtered samples toward a center of the passband.
Abstract translation: 公开了对信号进行滤波的装置和方法。 在这种装置中，外部多相滤波器被配置用于接收输入信号并将输入信号通道化为外部滤波的采样。 外部逆傅立叶变换块耦合到外部多相滤波器并且被配置用于将外部滤波的样本变换为粗略多径输出。 内部多相滤波器耦合到粗多路径输出的路径，用于从其接收信息，并被配置用于生成从路径获得的信息的内部滤波样本。 内部滤波的样本用于将与外部滤波样本相关联的通带的边缘移动到通带的中心。
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公开(公告)号：US09455760B1
公开(公告)日：2016-09-27
申请号：US14791096
申请日：2015-07-02
Applicant: Xilinx, Inc.
Inventor： Christopher H. Dick , Hemang M. Parekh , Hongzhi Zhao , Vincent C. Barnes
CPC classification number: H04B1/62 , H03F1/3247 , H03F3/245 , H03F2201/3233 , H04B1/0475 , H04B2001/0425 , H04L25/03343 , H04L27/368
Abstract: Apparatus, method therefor, generally related to signal preconditioning. In such an apparatus, a signal classifier block and a delay block are commonly coupled for receiving an input signal. The delay block is for providing a delayed version of the input signal. The signal classifier block is for classifying the input signal and generating a configuration signal having configuration information for digital predistortion (“DPD”) engine parameterization in response to the input signal classification. A DPD engine is for receiving the delayed version of the input signal and the configuration signal and for providing a predistorted output signal.
Abstract translation: 装置及其方法一般与信号预处理有关。 在这种装置中，信号分类器块和延迟块通常被耦合用于接收输入信号。 延迟块用于提供输入信号的延迟版本。 信号分类器块用于对输入信号进行分类，并产生具有响应于输入信号分类的用于数字预失真（“DPD”）引擎参数化的配置信息的配置信号。 DPD引擎用于接收输入信号和配置信号的延迟版本并提供预失真的输出信号。
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