公开(公告)号：US20240364569A1

公开(公告)日：2024-10-31

申请号：US18632062

申请日：2024-04-10

Applicant: Texas Instruments Incorporated

Inventor： Raju Kharataram Chaudhari ,  Aswath VS ,  Sriram Murali ,  Jaiganesh Balakrishnan ,  Sreenath Narayanan Potty ,  Kapil Kumar

IPC: H04L27/26 ,  H04B1/04

CPC classification number: H04L27/2618 ,  H04B1/0475

Abstract: An example apparatus includes: crest factor reduction circuitry having a signal input and a peak cancellation waveform input; and peak cancellation waveform generator circuitry including: carrier profile analyzer circuitry having a signal input coupled to the signal input of the crest factor reduction circuitry, and having a carrier profile output; waveform construction circuitry having a carrier profile input coupled to the carrier profile output of the carrier profile analyzer circuitry, having a second input, and having a peak cancellation waveform output coupled to the peak cancellation waveform input of the crest factor reduction circuitry; and profile change detector circuitry having a carrier profile input coupled to the carrier profile output of the carrier profile analyzer circuitry, and having an output coupled to the second input of the waveform construction circuitry.

公开(公告)号：US20240297621A1

公开(公告)日：2024-09-05

申请号：US18592045

申请日：2024-02-29

Applicant: Texas Instruments Incorporated

Inventor： Jawaharlal Tangudu ,  Goutham Ramesh ,  Sarma Sundareswara Gunturi ,  Harsh Garg ,  Jaiganesh Balakrishnan ,  Mathews John ,  Sashidharan Venkatraman ,  Sanjay Pennam

IPC: H03F1/32 ,  H03F3/21

CPC classification number: H03F1/3241 ,  H03F3/21 ,  H03F2201/3233

Abstract: An example method includes switching a first multiplexer circuit associated with first delay circuitry from (a) a first sub-lookup table (LUT) of a first LUT of digital pre-distortion (DPD) corrector circuitry to (b) a first corresponding sub-LUT of a second LUT of the DPD corrector circuitry, the first sub-LUT associated with the first delay circuitry, the second LUT storing updated values to compensate for non-linearity of power amplifier circuitry of a transmitter including the DPD corrector circuitry. The method includes, based on a value of a counter being equal to a difference between (1) a first delay of the first delay circuitry and (2) a second delay of second delay circuitry, switching a second multiplexer circuit associated with the second delay circuitry from (a) a second sub-LUT of the first LUT to (b) a second corresponding sub-LUT of the second LUT, the second sub-LUT associated with the second delay circuitry.

公开(公告)号：US12074622B2

公开(公告)日：2024-08-27

申请号：US18318800

申请日：2023-05-17

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Jaiganesh Balakrishnan

IPC: H04B1/12 ,  H04B1/10 ,  H04B1/16 ,  H04B17/20 ,  H04B17/318 ,  H04B17/336 ,  H04H40/72

CPC classification number: H04B1/12 ,  H04B1/10 ,  H04B1/1027 ,  H04B1/1646 ,  H04B17/20 ,  H04B17/318 ,  H04B17/336 ,  H04H40/72 ,  H04B2001/1054

Abstract: A wireless receiver includes a down converter module operable to deliver a signal having a signal bandwidth that changes over time, a dynamically controllable filter module having a filter bandwidth and fed by said down converter module, and a measurement module operable to at least approximately measure the signal bandwidth, said dynamically controllable filter module responsive to said measurement module to dynamically adjust the filter bandwidth to more nearly match the signal bandwidth as it changes over time, whereby output from said filter module is noise-reduced. Other wireless receivers, electronic circuits, and processes for their operation are disclosed.

公开(公告)号：US11695440B2

公开(公告)日：2023-07-04

申请号：US17530158

申请日：2021-11-18

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Jaiganesh Balakrishnan

IPC: H04B1/12 ,  H04B1/16 ,  H04H40/72 ,  H04B17/318 ,  H04B17/20 ,  H04B17/336 ,  H04B1/10

CPC classification number: H04B1/12 ,  H04B1/10 ,  H04B1/1027 ,  H04B1/1646 ,  H04B17/20 ,  H04B17/318 ,  H04B17/336 ,  H04H40/72 ,  H04B2001/1054

Abstract: A wireless receiver (10) includes a down converter module (210) operable to deliver a signal having a signal bandwidth that changes over time, a dynamically controllable filter module (200) having a filter bandwidth and fed by said down converter module (210), and a measurement module (295) operable to at least approximately measure the signal bandwidth, said dynamically controllable filter module (200) responsive to said measurement module (295) to dynamically adjust the filter bandwidth to more nearly match the signal bandwidth as it changes over time, whereby output from said filter module (200) is noise-reduced. Other wireless receivers, electronic circuits, and processes for their operation are disclosed.

公开(公告)号：US11581873B2

公开(公告)日：2023-02-14

申请号：US17463317

申请日：2021-08-31

Applicant: Texas Instruments Incorporated

Inventor： Jaiganesh Balakrishnan ,  Sriram Murali ,  Kalyan Gudipati ,  Venkateshwara Reddy Pothapu ,  Sarma Sundareswara Gunturi

IPC: H03H11/00 ,  H03H11/04 ,  H03H17/00

Abstract: Dual mode filters having two reconfigurable multi-stage filters. In a dual band mode, each reconfigurable filter filters an input signal in a different band using every filter stage. In a single band mode, both reconfigurable filters are effectively divided into two sub-chains that include either the odd-numbered filter stages or the even-numbered filter stages. Together, the four sub-chains in the single band mode filter an input signal in a single band with a higher parallelization than each reconfigurable filter in the dual band mode. In some embodiments, the dual mode filter is a decimation filter. In other embodiments, the dual mode filter is a resampling filter. In still other embodiments, the dual mode filter is an interpolation filter.

公开(公告)号：US11171681B2

公开(公告)日：2021-11-09

申请号：US17072104

申请日：2020-10-16

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Sriram Murali ,  Jaiganesh Balakrishnan ,  Pooja Sundar ,  Harshavardhan Adepu ,  Wenjing Lu ,  Yeswanth Guntupalli

IPC: H04B1/40 ,  H04B1/00

Abstract: A digital up-converter (DUC) includes conjugate-mixer-combiner. The conjugate-mixer-combiner includes a pre-combiner configured to generate combinations of a first in-phase (I) value to be transmitted at a first frequency of a first frequency band, a first quadrature (Q) value to be transmitted at the first frequency of a first frequency band, a second I value for to be transmitted at a second frequency of a second frequency band, and a second Q value to be transmitted at the second frequency of a second frequency band. The conjugate-mixer-combiner further includes a plurality of multipliers collectively configured to shift the combinations based on an average difference between the first frequency and the second frequency.

公开(公告)号：US11139916B2

公开(公告)日：2021-10-05

申请号：US16936065

申请日：2020-07-22

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Sanjay Pennam ,  Vamsi Krishna Kandalla ,  Brahmendra Reddy Yatham ,  Shailesh Wardhen ,  Jaiganesh Balakrishnan ,  Jawaharlal Tangudu

IPC: H04L1/00 ,  H04B1/04

Abstract: A transmitter includes a data stream encoder layer having an output and a pattern generator having a bit pattern output. The transmitter further includes a first multiplexer having first and second inputs and a first multiplexer output. The first input is coupled to the output of the data stream encoder layer, and the second input is coupled to the bit pattern output of the pattern generator. While at least a portion of the data stream encoder layer is powered down, the pattern generator is configured to provide bit patterns on its bit pattern output, a control signal to the first multiplexer is configured to select the second input of the first multiplexer, and the first multiplexer is configured to output the bit patterns on the output of the first multiplexer.

公开(公告)号：US20210083695A1

公开(公告)日：2021-03-18

申请号：US17022871

申请日：2020-09-16

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Jaiganesh Balakrishnan ,  Sriram Murali ,  Sundarrajan Rangachari ,  Yeswanth Guntupalli

IPC: H04B1/00

Abstract: A radio-frequency (RF) sampling transmitter (e.g., of the type that may be used in 5G wireless base stations) includes a complex baseband digital-to-analog converter (DAC) response compensator that operates on a complex baseband signal at a sampling rate lower than the sampling rate of an RF sampling DAC in the RF sampling transmitter. The DAC response compensator flattens the sample-and-hold response of the RF sampling DAC only in the passband of interest, addressing the problem of a sinc response introduced by the sample-and-hold operation of the RF sampling DAC and avoiding the architectural complexity and high power consumption of an inverse sinc filter that operates on the signal at a point in the signal chain after it has already been up-converted to an RF passband.

公开(公告)号：US10930362B2

公开(公告)日：2021-02-23

申请号：US16916911

申请日：2020-06-30

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Aravind Ganesan ,  Jaiganesh Balakrishnan ,  Nagarajan Viswanathan ,  Yeswanth Guntupalli ,  Ajai Paulose ,  Mathews John ,  Jagannathan Venkataraman ,  Neeraj Shrivastava

IPC: G11C29/02 ,  G11C17/18 ,  G11C17/16 ,  G11C17/14

Abstract: A one-time write, read-only memory for storing trimming parameters includes an address pointer table, a fixed packet portion, and a flexible packet portion. The fixed packet portion includes one or more fixed packets, each fixed packet including trimming parameters for a component identified for trimming during a design phase. The flexible packet portion includes one or more flexible packets of different types. Each flexible packet includes trimming parameters for a component identified for trimming after the design phase. One packet type includes a length section and a number of fields equal to a value stored in the length section. Each field includes an address, a trimming parameter, and a mask. Another packet type includes trimming parameters associated with operands in operating instructions for a microcontroller, where the operands include an address and a mask.

公开(公告)号：US10911161B2

公开(公告)日：2021-02-02

申请号：US16697236

申请日：2019-11-27

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Sandeep Oswal ,  Visvesvaraya Pentakota ,  Jagannathan Venkataraman ,  Jaiganesh Balakrishnan ,  Francesco Dantoni

IPC: H04B17/13 ,  H04B1/04 ,  H04L27/36

Abstract: A transmitter for an RF communications system, that includes an auxiliary receiver for capturing transmit signal data for use in compensating/correcting transmit signal impairments (such as for DPD, QMC, LOL). The transmitter (such as Zero IF) includes analog chain elements that introduce transmit signal impairments (such as PA nonlinearities). The auxiliary receiver is configured to receive loopback transmit RF signals, and includes an RF direct sampling ADC to convert the loopback transmit RF signals to digital transmit RF signals. Digital down conversion circuitry is configured to downconvert the digital transmit RF signals to captured digital transmit baseband signals, and data capture circuitry is configured to generate the transmit signal data based on the captured digital transmit baseband signals.