公开(公告)号：US10741268B2

公开(公告)日：2020-08-11

申请号：US16235698

申请日：2018-12-28

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Aravind Ganesan ,  Jaiganesh Balakrishnan ,  Nagarajan Viswanathan ,  Yeswanth Guntupalli ,  Ajai Paulose ,  Mathews John ,  Jagannathan Venkataraman ,  Neeraj Shrivastava

IPC: G11C29/02 ,  G11C17/14 ,  G11C17/16 ,  G11C17/18

Abstract: A one-time write, read-only memory for storing trimming parameters includes an address pointer table, a fixed packet portion, and a flexible packet portion. The fixed packet portion includes one or more fixed packets, each fixed packet including trimming parameters for a component identified for trimming during a design phase. The flexible packet portion includes one or more flexible packets of different types. Each flexible packet includes trimming parameters for a component identified for trimming after the design phase. One packet type includes a length section and a number of fields equal to a value stored in the length section. Each field includes an address, a trimming parameter, and a mask. Another packet type includes trimming parameters associated with operands in operating instructions for a microcontroller, where the operands include an address and a mask.

公开(公告)号：US11239854B2

公开(公告)日：2022-02-01

申请号：US17061730

申请日：2020-10-02

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Jawaharlal Tangudu ,  Pankaj Gupta ,  Sreenath Narayanan Potty ,  Ajai Paulose ,  Chandrasekhar Sriram ,  Mahesh Ravi Varma ,  Shabbar Abbasi Vejlani ,  Neeraj Shrivastava ,  Himanshu Varshney ,  Divyeshkumar Mahendrabhai Patel ,  Raju Kharataram Chaudhari

IPC: H03M1/36 ,  H03M1/12

Abstract: A non-linearity correction circuit includes a non-linearity coefficient estimation circuit. The non-linearity coefficient estimation circuit includes a data capture circuit, a non-linearity term generation circuit, a time-to-frequency conversion circuit, a bin identification circuit, a residual non-linearity conversion circuit, and a non-linearity coefficient generation circuit. The non-linearity term generation circuit is coupled to the data capture circuit. The time-to-frequency conversion circuit is coupled to the data capture circuit and the non-linearity term generation circuit. The bin identification circuit is coupled to the time-to-frequency conversion circuit. The residual non-linearity conversion circuit is coupled to the bin identification circuit. The non-linearity coefficient generation circuit is coupled to the bin identification circuit and the residual non-linearity conversion circuit.

公开(公告)号：US20210105019A1

公开(公告)日：2021-04-08

申请号：US17063037

申请日：2020-10-05

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Pankaj Gupta ,  Jawaharlal Tangudu ,  Ajai Paulose

IPC: H03M1/10

Abstract: A method for non-linearity correction includes receiving a first output signal from a data signal path containing a first analog-to-digital converter and receiving a second output signal from a second analog-to-digital converter. The method also includes generating first non-linearity coefficients using the first output signal and generating second non-linearity coefficients using the first and second output signals. The method further includes applying, by a non-linearity corrector in the data signal path, the first and second non-linearity coefficients to compensate for non-linearity components in a digitized signal output from the first analog-to-digital converter to generate a corrected digitized signal.

公开(公告)号：US10930362B2

公开(公告)日：2021-02-23

申请号：US16916911

申请日：2020-06-30

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Aravind Ganesan ,  Jaiganesh Balakrishnan ,  Nagarajan Viswanathan ,  Yeswanth Guntupalli ,  Ajai Paulose ,  Mathews John ,  Jagannathan Venkataraman ,  Neeraj Shrivastava

IPC: G11C29/02 ,  G11C17/18 ,  G11C17/16 ,  G11C17/14

Abstract: A one-time write, read-only memory for storing trimming parameters includes an address pointer table, a fixed packet portion, and a flexible packet portion. The fixed packet portion includes one or more fixed packets, each fixed packet including trimming parameters for a component identified for trimming during a design phase. The flexible packet portion includes one or more flexible packets of different types. Each flexible packet includes trimming parameters for a component identified for trimming after the design phase. One packet type includes a length section and a number of fields equal to a value stored in the length section. Each field includes an address, a trimming parameter, and a mask. Another packet type includes trimming parameters associated with operands in operating instructions for a microcontroller, where the operands include an address and a mask.

公开(公告)号：US12184455B2

公开(公告)日：2024-12-31

申请号：US18049865

申请日：2022-10-26

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Aravind Ganesan ,  Ajai Paulose ,  Ankush G. P.

IPC: H04L25/03

Abstract: A method for adapting a continuous time equalizer (CTE) includes determining a gain of a discrete time equalizer (DTE) and determining whether the gain has increased or decreased by more than the threshold amount. Responsive to determining that the gain has increased or decreased by more than the threshold amount, the method includes sequentially configuring the CTE for multiple CTE settings such that gain of the CTE is caused to increase or decrease in a same direction with the change in gain of the DTE. The method also includes determining a separate figure of merit (FOM) for each of the multiple CTE settings and selecting a new CTE setting from the multiple CTE settings based on the FOM for each of the multiple CTE settings.

公开(公告)号：US20230275594A1

公开(公告)日：2023-08-31

申请号：US17682753

申请日：2022-02-28

Applicant: Texas Instruments Incorporated

Inventor： Pankaj Gupta ,  Ajai Paulose ,  Sreenath Narayanan Potty ,  Divyansh Jain ,  Jaiganesh Balakrishnan ,  Jawaharlal Tangudu ,  Aswath VS ,  Girish Nadiger ,  Ankur Jain

IPC: H03M1/06

CPC classification number: H03M1/0617

Abstract: An example apparatus includes: nonlinearity function selection circuitry with an output, the nonlinearity function selection circuitry to select a type of a nonlinearity function, the nonlinearity function to model nonlinearity portions of data output from an analog-to-digital converter, nonlinearity function term generation circuitry with a first input coupled to the output, the nonlinearity function term generation circuitry to generate one or more nonlinearity function terms of the nonlinearity function based on the type of the nonlinearity function and the data, and coefficient determination circuitry with a second input coupled to the output, the coefficient determination circuitry to determine one or more nonlinearity function coefficients based on the one or more nonlinearity function terms, the nonlinearity portions of the data to be compensated based on the one or more nonlinearity function coefficients.

公开(公告)号：US12057854B2

公开(公告)日：2024-08-06

申请号：US17682753

申请日：2022-02-28

Applicant: Texas Instruments Incorporated

Inventor： Pankaj Gupta ,  Ajai Paulose ,  Sreenath Narayanan Potty ,  Divyansh Jain ,  Jaiganesh Balakrishnan ,  Jawaharlal Tangudu ,  Aswath VS ,  Girish Nadiger ,  Ankur Jain

IPC: H03M1/06

CPC classification number: H03M1/0617

Abstract: An example apparatus includes: nonlinearity function selection circuitry with an output, the nonlinearity function selection circuitry to select a type of a nonlinearity function, the nonlinearity function to model nonlinearity portions of data output from an analog-to-digital converter, nonlinearity function term generation circuitry with a first input coupled to the output, the nonlinearity function term generation circuitry to generate one or more nonlinearity function terms of the nonlinearity function based on the type of the nonlinearity function and the data, and coefficient determination circuitry with a second input coupled to the output, the coefficient determination circuitry to determine one or more nonlinearity function coefficients based on the one or more nonlinearity function terms, the nonlinearity portions of the data to be compensated based on the one or more nonlinearity function coefficients.

公开(公告)号：US20240146584A1

公开(公告)日：2024-05-02

申请号：US18049865

申请日：2022-10-26

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Aravind Ganesan ,  Ajai Paulose ,  Ankush G.P.

IPC: H04L25/03

CPC classification number: H04L25/03076

Abstract: A method for adapting a continuous time equalizer (CTE) includes determining a gain of a discrete time equalizer (DTE) and determining whether the gain has increased or decreased by more than the threshold amount. Responsive to determining that the gain has increased or decreased by more than the threshold amount, the method includes sequentially configuring the CTE for multiple CTE settings such that gain of the CTE is caused to increase or decrease in a same direction with the change in gain of the DTE. The method also includes determining a separate figure of merit (FOM) for each of the multiple CTE settings and selecting a new CTE setting from the multiple CTE settings based on the FOM for each of the multiple CTE settings.

公开(公告)号：US20220229961A1

公开(公告)日：2022-07-21

申请号：US17411262

申请日：2021-08-25

Applicant: Texas Instruments Incorporated

Inventor： Ajai Paulose ,  Aravind Ganesan ,  Sashidharan Venkatraman ,  Jaiganesh Balakrishnan

IPC: G06F30/34 ,  G06F16/174

Abstract: A system for programming an eFuse array in an integrated circuit (IC) includes an eFuse data file which has a first plurality of bits. The system includes a data compression module which has an input coupled to receive the eFuse data file. The data compression module reduces the size of the eFuse data file and provides a compressed data file. The compressed data file has fewer bits than the eFuse data file. The system includes an eFuse controller which has an input coupled to receive the compressed data file. The eFuse controller programs the eFuse array to permanently store the compressed data file in the eFuse array.

公开(公告)号：US11251803B2

公开(公告)日：2022-02-15

申请号：US17063037

申请日：2020-10-05

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Pankaj Gupta ,  Jawaharlal Tangudu ,  Ajai Paulose

IPC: H03M1/06 ,  H03M1/10 ,  H03M3/00 ,  H03M1/12

Abstract: A method for non-linearity correction includes receiving a first output signal from a data signal path containing a first analog-to-digital converter and receiving a second output signal from a second analog-to-digital converter. The method also includes generating first non-linearity coefficients using the first output signal and generating second non-linearity coefficients using the first and second output signals. The method further includes applying, by a non-linearity corrector in the data signal path, the first and second non-linearity coefficients to compensate for non-linearity components in a digitized signal output from the first analog-to-digital converter to generate a corrected digitized signal.