公开(公告)号：US20230275594A1

公开(公告)日：2023-08-31

申请号：US17682753

申请日：2022-02-28

Applicant: Texas Instruments Incorporated

Inventor： Pankaj Gupta ,  Ajai Paulose ,  Sreenath Narayanan Potty ,  Divyansh Jain ,  Jaiganesh Balakrishnan ,  Jawaharlal Tangudu ,  Aswath VS ,  Girish Nadiger ,  Ankur Jain

IPC: H03M1/06

CPC classification number: H03M1/0617

Abstract: An example apparatus includes: nonlinearity function selection circuitry with an output, the nonlinearity function selection circuitry to select a type of a nonlinearity function, the nonlinearity function to model nonlinearity portions of data output from an analog-to-digital converter, nonlinearity function term generation circuitry with a first input coupled to the output, the nonlinearity function term generation circuitry to generate one or more nonlinearity function terms of the nonlinearity function based on the type of the nonlinearity function and the data, and coefficient determination circuitry with a second input coupled to the output, the coefficient determination circuitry to determine one or more nonlinearity function coefficients based on the one or more nonlinearity function terms, the nonlinearity portions of the data to be compensated based on the one or more nonlinearity function coefficients.

公开(公告)号：US20240143282A1

公开(公告)日：2024-05-02

申请号：US17977813

申请日：2022-10-31

Applicant: Texas Instruments Incorporated

Inventor： Mathews John ,  Jawaharlal Tangudu ,  Pankaj Gaur ,  Divyansh Jain ,  Pankaj Gupta

IPC: G06F7/57 ,  G06F17/16

CPC classification number: G06F7/57 ,  G06F17/16

Abstract: In described examples, an integrated circuit includes an output terminal coupled to an input of a power amplifier, a feedback terminal coupled to an output of the power amplifier, a data terminal that receives a data stream, and a digital pre-distortion (DPD) circuit. The DPD circuit includes a capture circuit, a DPD estimator responsive to the data stream and the feedback terminal, and a DPD corrector responsive to the DPD estimator. The DPD estimator includes an instruction memory configured to store instructions and a vector arithmetic processing unit (APU) coupled to the instruction memory. The vector APU includes vector memories, vector arithmetic blocks, and an instruction decode block. The vector arithmetic blocks include vector addition blocks and vector multiplication blocks. The instruction decode block is configured to cause the vector APU to perform complex domain vector arithmetic on vectors stored in the vector memories in response to the instructions.

公开(公告)号：US12057854B2

公开(公告)日：2024-08-06

申请号：US17682753

申请日：2022-02-28

Applicant: Texas Instruments Incorporated

Inventor： Pankaj Gupta ,  Ajai Paulose ,  Sreenath Narayanan Potty ,  Divyansh Jain ,  Jaiganesh Balakrishnan ,  Jawaharlal Tangudu ,  Aswath VS ,  Girish Nadiger ,  Ankur Jain

IPC: H03M1/06

CPC classification number: H03M1/0617

Abstract: An example apparatus includes: nonlinearity function selection circuitry with an output, the nonlinearity function selection circuitry to select a type of a nonlinearity function, the nonlinearity function to model nonlinearity portions of data output from an analog-to-digital converter, nonlinearity function term generation circuitry with a first input coupled to the output, the nonlinearity function term generation circuitry to generate one or more nonlinearity function terms of the nonlinearity function based on the type of the nonlinearity function and the data, and coefficient determination circuitry with a second input coupled to the output, the coefficient determination circuitry to determine one or more nonlinearity function coefficients based on the one or more nonlinearity function terms, the nonlinearity portions of the data to be compensated based on the one or more nonlinearity function coefficients.