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公开(公告)号：US10419010B1
公开(公告)日：2019-09-17
申请号：US16217165
申请日：2018-12-12
摘要： Pipelined analog-to-digital converters (ADCs) include a flash ADC that reduces noise tones in power supply current drawn by the flash ADC. A pipelined analog-to-digital converter (ADC) includes a flash ADC and error correction circuitry coupled to the flash ADC. The flash ADC includes a plurality of latched comparators and a plurality of driver circuits. Each of the latched comparators includes an inverting output and a non-inverting output. Each of the driver circuits is coupled to one of the latched comparators, and includes an input terminal and an output terminal. In a first subset of the driver circuits the input terminal is coupled to the inverting output of one of the latched comparators. In a second subset of the driver circuits the input terminal is coupled to the non-inverting output of one of the latched comparators.
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公开(公告)号：US20240187013A1
公开(公告)日：2024-06-06
申请号：US18440113
申请日：2024-02-13
发明人： Himanshu Varshney , Viswanathan Nagarajan , Charls Babu , Narasimhan Rajagopal , Eeshan Miglani , Visvesvaraya A. Pentakota
CPC分类号： H03M1/1009 , H03M1/002 , H03M1/10 , H03M1/12
摘要： In described examples, an analog to digital converter (ADC), having an input operable to receive an analog signal and an output operable to output a digital representation of the analog signal, includes a voltage to delay (VD) block. The VD block is coupled to the input of the ADC and generates a delay signal responsive to a calibration signal. A backend ADC is coupled to the VD block, and receives the delay signal. The backend ADC having multiple stages including a first stage. A calibration engine is coupled to the multiple stages and the VD block. The calibration engine measures an error count of the first stage and stores a delay value of the first stage for which the error count is minimum.
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公开(公告)号：US11962318B2
公开(公告)日：2024-04-16
申请号：US17568972
申请日：2022-01-05
发明人： Himanshu Varshney , Viswanathan Nagarajan , Charls Babu , Narasimhan Rajagopal , Eeshan Miglani , Visvesvaraya A Pentakota
CPC分类号： H03M1/1009 , H03M1/002 , H03M1/10 , H03M1/12
摘要： In described examples, an analog to digital converter (ADC), having an input operable to receive an analog signal and an output operable to output a digital representation of the analog signal, includes a voltage to delay (VD) block. The VD block is coupled to the input of the ADC and generates a delay signal responsive to a calibration signal. A backend ADC is coupled to the VD block, and receives the delay signal. The backend ADC having multiple stages including a first stage. A calibration engine is coupled to the multiple stages and the VD block. The calibration engine measures an error count of the first stage and stores a delay value of the first stage for which the error count is minimum.
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公开(公告)号：US09548752B1
公开(公告)日：2017-01-17
申请号：US15048027
申请日：2016-02-19
发明人： Neeraj Shrivastava , Supreet Joshi , Himanshu Varshney , Jafar Sadique Kaviladath , Visvesvaraya Pentakota , Shagun Dusad
CPC分类号： H03M1/1009 , H03M1/1019 , H03M1/1057 , H03M1/66 , H03M1/742 , H03M1/745 , H03M1/785
摘要： The disclosure provides a current steering digital to analog converter (DAC) that includes a plurality of DAC elements. At least one DAC element of the plurality of DAC elements is coupled to a calibration circuit. The calibration circuit includes a fixed current source coupled to a primary node of the DAC element through a first estimation switch. A digital code generator is coupled to the primary node, and generates a first digital code corresponding to a primary voltage generated at the primary node. The digital code generator generates a second digital code. A correction DAC is coupled to the digital code generator and generates a bias voltage based on the second digital code. The bias voltage is provided to the DAC element such that a current flowing through each DAC element of the plurality of DAC elements is equal.
摘要翻译： 本公开提供了包括多个DAC元件的电流转向数模转换器（DAC）。 多个DAC元件中的至少一个DAC元件耦合到校准电路。 校准电路包括通过第一估计开关耦合到DAC元件的主节点的固定电流源。 数字码发生器耦合到主节点，并且产生对应于在主节点处产生的主电压的第一数字码。 数字代码生成器产生第二数字代码。 校正DAC耦合到数字代码发生器并且基于第二数字代码产生偏置电压。 偏置电压被提供给DAC元件，使得流过多个DAC元件中的每个DAC元件的电流相等。
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公开(公告)号：US20220224349A1
公开(公告)日：2022-07-14
申请号：US17568972
申请日：2022-01-05
发明人： Himanshu Varshney , Viswanathan Nagarajan , Charls Babu , Narasimhan Rajagopal , Eeshan Miglani , Visvesvaraya A. Pentakota
IPC分类号： H03M1/10
摘要： In described examples, an analog to digital converter (ADC), having an input operable to receive an analog signal and an output operable to output a digital representation of the analog signal, includes a voltage to delay (VD) block. The VD block is coupled to the input of the ADC and generates a delay signal responsive to a calibration signal. A backend ADC is coupled to the VD block, and receives the delay signal. The backend ADC having multiple stages including a first stage. A calibration engine is coupled to the multiple stages and the VD block. The calibration engine measures an error count of the first stage and stores a delay value of the first stage for which the error count is minimum.
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公开(公告)号：US11784660B2
公开(公告)日：2023-10-10
申请号：US17589533
申请日：2022-01-31
CPC分类号： H03M1/502 , H03M1/1009 , H03M1/362
摘要： In an example, a system includes an input channel and a voltage to delay converter (V2D) coupled to the input channel. The system also includes a first multiplexer coupled to the V2D and an analog-to-digital converter (ADC) coupled to the first multiplexer. The system includes a second multiplexer coupled to the input channel and an auxiliary ADC coupled to the second multiplexer. The system includes calibration circuitry coupled to an output of the auxiliary ADC, where the calibration circuitry is configured to correct a non-linearity in a signal provided by the input channel. The calibration circuitry is also configured to determine the non-linearity of the signal provided to the ADC relative to the signal provided to the auxiliary ADC.
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公开(公告)号：US11239854B2
公开(公告)日：2022-02-01
申请号：US17061730
申请日：2020-10-02
发明人： Jawaharlal Tangudu , Pankaj Gupta , Sreenath Narayanan Potty , Ajai Paulose , Chandrasekhar Sriram , Mahesh Ravi Varma , Shabbar Abbasi Vejlani , Neeraj Shrivastava , Himanshu Varshney , Divyeshkumar Mahendrabhai Patel , Raju Kharataram Chaudhari
摘要： A non-linearity correction circuit includes a non-linearity coefficient estimation circuit. The non-linearity coefficient estimation circuit includes a data capture circuit, a non-linearity term generation circuit, a time-to-frequency conversion circuit, a bin identification circuit, a residual non-linearity conversion circuit, and a non-linearity coefficient generation circuit. The non-linearity term generation circuit is coupled to the data capture circuit. The time-to-frequency conversion circuit is coupled to the data capture circuit and the non-linearity term generation circuit. The bin identification circuit is coupled to the time-to-frequency conversion circuit. The residual non-linearity conversion circuit is coupled to the bin identification circuit. The non-linearity coefficient generation circuit is coupled to the bin identification circuit and the residual non-linearity conversion circuit.
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