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公开(公告)号：US11239854B2
公开(公告)日：2022-02-01
申请号：US17061730
申请日：2020-10-02
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Jawaharlal Tangudu , Pankaj Gupta , Sreenath Narayanan Potty , Ajai Paulose , Chandrasekhar Sriram , Mahesh Ravi Varma , Shabbar Abbasi Vejlani , Neeraj Shrivastava , Himanshu Varshney , Divyeshkumar Mahendrabhai Patel , Raju Kharataram Chaudhari
Abstract: A non-linearity correction circuit includes a non-linearity coefficient estimation circuit. The non-linearity coefficient estimation circuit includes a data capture circuit, a non-linearity term generation circuit, a time-to-frequency conversion circuit, a bin identification circuit, a residual non-linearity conversion circuit, and a non-linearity coefficient generation circuit. The non-linearity term generation circuit is coupled to the data capture circuit. The time-to-frequency conversion circuit is coupled to the data capture circuit and the non-linearity term generation circuit. The bin identification circuit is coupled to the time-to-frequency conversion circuit. The residual non-linearity conversion circuit is coupled to the bin identification circuit. The non-linearity coefficient generation circuit is coupled to the bin identification circuit and the residual non-linearity conversion circuit.
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公开(公告)号：US20240364569A1
公开(公告)日：2024-10-31
申请号：US18632062
申请日：2024-04-10
Applicant: Texas Instruments Incorporated
Inventor： Raju Kharataram Chaudhari , Aswath VS , Sriram Murali , Jaiganesh Balakrishnan , Sreenath Narayanan Potty , Kapil Kumar
CPC classification number: H04L27/2618 , H04B1/0475
Abstract: An example apparatus includes: crest factor reduction circuitry having a signal input and a peak cancellation waveform input; and peak cancellation waveform generator circuitry including: carrier profile analyzer circuitry having a signal input coupled to the signal input of the crest factor reduction circuitry, and having a carrier profile output; waveform construction circuitry having a carrier profile input coupled to the carrier profile output of the carrier profile analyzer circuitry, having a second input, and having a peak cancellation waveform output coupled to the peak cancellation waveform input of the crest factor reduction circuitry; and profile change detector circuitry having a carrier profile input coupled to the carrier profile output of the carrier profile analyzer circuitry, and having an output coupled to the second input of the waveform construction circuitry.
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Patent Agency Ranking
公开(公告)号：US10924320B2
公开(公告)日：2021-02-16
申请号：US16525103
申请日：2019-07-29
Applicant: TEXAS INSTRUMENTS INCORPORATED
Abstract: An IQ estimation module comprising a powerup state IQ estimator configured to generate powerup state IQ estimates based on a powerup calibration of the IQ estimation module, a steady state IQ estimator configured to generate steady state IQ estimates during a steady state operation of the IQ estimation module, and an IQ estimate extender configured to determine differences between the powerup state IQ estimates and steady state IQ estimates at their respective frequency bins and adjust the powerup state IQ estimates to improve the accuracy of IQ estimates.
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4.发明申请公开(公告)号：US20250047531A1
公开(公告)日：2025-02-06
申请号：US18651130
申请日：2024-04-30
Applicant: Texas Instruments Incorporated
Inventor： Jaiganesh Balakrishnan , Aswath VS , Sriram Murali , Sreenath Narayanan Potty , Raju Kharataram Chaudhari , Kapil Kumar
Abstract: An example apparatus described herein to implement cancellation pulse generation includes a first memory storing first subsets of data samples of a single pulse cancellation waveform. The example apparatus includes a second memory storing second subsets of data samples of the single pulse cancellation waveform, the second subsets including different data samples of the single pulse cancellation waveform than the first subsets. The example apparatus includes first circuitry coupled to the first memory and to the second memory in parallel. The example apparatus includes a plurality of buffers. The example apparatus includes second circuitry coupled to the plurality of buffers.
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公开(公告)号：US11757479B2
公开(公告)日：2023-09-12
申请号：US17489381
申请日：2021-09-29
Applicant: Texas Instruments Incorporated
Inventor： Sarma Sundareswara Gunturi , Venkateshwara Reddy Pothapu , Chandrasekhar Sriram , Raju Kharataram Chaudhari , Sai Vaibhav Batchu , Pankaj Gaur
CPC classification number: H04B1/0475 , H03G3/3036 , H03G2201/106
Abstract: A TX-TX pre-compensation system that estimates unwanted coupling in a victim transmit chain caused by an aggressor transmit chain and injects a pre-compensation signal to cancel out the estimated coupling. In some embodiments, a signal measurement module estimates the amplitude, phase, and envelope delay of the coupling and an isolation pre-compensation module generates the pre-compensation signal based on the estimated amplitude, the estimated phase, the estimated envelope delay, and the difference between the carrier frequencies of the transmit chains. Since the phase of the coupling may be affected by the carrier frequency of the transmit chains, in some embodiments the phase of the pre-compensation signal is adjusted in response to a change in carrier frequency. Since the amplitude of the coupling may be affected by attenuator gain settings, in some embodiments the amplitude of the pre-compensation signal may be adjusted in response to a change in attenuator gain setting.
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公开(公告)号：US11356125B2
公开(公告)日：2022-06-07
申请号：US16953947
申请日：2020-11-20
Applicant: Texas Instruments Incorporated
Inventor： Jawaharlal Tangudu , Yeswanth Guntupalli , Kalyan Gudipati , Robert Clair Keller , Wenjing Lu , Jaiganesh Balakrishnan , Harsh Garg , Bragadeesh S , Raju Kharataram Chaudhari , Francesco Dantoni
Abstract: An integrated circuit comprises an input, a digital step attenuator, an analog-to-digital converter, a first output, a second output, a first bandwidth filter, a first band attack detector, a first band decay detector, a second bandwidth filter, a second band attack detector, a second band decay detector, and an automatic gain control. The ADC is configured to output a digital signal including a first and a second frequency range. The first and second bandwidth filters are configured to extract respective digital signals comprising the first and second frequency ranges. The band attack and decay detectors are configured to detect band peaks or decays thereof such that the DSA and External AMP may be controlled by means of the AGC based on the detected band peaks or decays, and ADC attack and ADC decay.
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公开(公告)号：US20210159924A1
公开(公告)日：2021-05-27
申请号：US16953947
申请日：2020-11-20
Applicant: Texas Instruments Incorporated
Inventor： Jawaharlal Tangudu , Yeswanth Guntupalli , Kalyan Gudipati , Robert Clair Keller , Wenjing Lu , Jaiganesh Balakrishnan , Harsh Garg , Bragadeesh S , Raju Kharataram Chaudhari , Francesco Dantoni
Abstract: An integrated circuit comprises an input, a digital step attenuator, an analog-to-digital converter, a first output, a second output, a first bandwidth filter, a first band attack detector, a first band decay detector, a second bandwidth filter, a second band attack detector, a second band decay detector, and an automatic gain control. The ADC is configured to output a digital signal including a first and a second frequency range. The first and second bandwidth filters are configured to extract respective digital signals comprising the first and second frequency ranges. The band attack and decay detectors are configured to detect band peaks or decays thereof such that the DSA and External AMP may be controlled by means of the AGC based on the detected band peaks or decays, and ADC attack and ADC decay.
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