公开(公告)号：US20110175110A1

公开(公告)日：2011-07-21

申请号：US13120890

申请日：2010-03-23

Applicant: Keiji Wada ,  Shin Harada ,  Takeyoshi Masuda ,  Misako Honaga

Inventor： Keiji Wada ,  Shin Harada ,  Takeyoshi Masuda ,  Misako Honaga

IPC: H01L29/24 ,  H01L21/336 ,  B82Y99/00 ,  B82Y40/00

CPC classification number: H01L29/045 ,  H01L29/1608 ,  H01L29/66068 ,  H01L29/78

Abstract: A MOSFET includes a silicon carbide (SiC) substrate having a main surface having an off angle of not less than 50° and not more than 65° relative to a {0001} plane; a semiconductor layer formed on the main surface of the SiC substrate; and an insulating film formed in contact with a surface of the semiconductor layer. When the insulating film has a thickness of not less than 30 nm and not more than 46 nm, the threshold voltage thereof is not more than 2.3V. When the insulating film has a thickness of more than 46 nm and not more than 100 nm, the threshold voltage thereof is more than 2.3 V and not more than 4.9 V.

Abstract translation: MOSFET包括碳化硅（SiC）基板，其具有相对于{0001}面具有不小于50°且不大于65°的偏离角的主表面; 形成在所述SiC衬底的主表面上的半导体层; 以及与半导体层的表面接触形成的绝缘膜。 当绝缘膜的厚度不小于30nm且不大于46nm时，其阈值电压不大于2.3V。 当绝缘膜的厚度大于46nm且不大于100nm时，其阈值电压大于2.3V且不大于4.9V。

公开(公告)号：US07846491B2

公开(公告)日：2010-12-07

申请号：US11664318

申请日：2006-03-02

Applicant: Takeyoshi Masuda

Inventor： Takeyoshi Masuda

IPC: B32B43/00

CPC classification number: C23C16/24 ,  C23C14/185 ,  C30B29/36 ,  C30B33/02

Abstract: A surface reconstruction method for a silicon carbide substrate includes a silicon film forming step of forming a silicon film on a surface of the silicon carbide substrate and a heat treatment step of heat-treating the silicon carbide substrate and the silicon film without providing a polycrystalline silicon carbide substrate on a surface of the silicon film. Here, after the heat treatment step, a silicon film removal step of removing the silicon film may be included. Further, a silicon oxide film forming step of oxidizing the silicon film after the heat treatment step to generate a silicon oxide film, and a silicon oxide film removal step of removing the silicon oxide film may be included.

Abstract translation: 碳化硅衬底的表面重建方法包括在碳化硅衬底的表面上形成硅膜的硅膜形成步骤和不提供多晶硅的碳化硅衬底和硅膜的热处理步骤 在硅膜的表面上的碳化物衬底。 这里，在热处理步骤之后，可以包括去除硅膜的硅膜去除步骤。 此外，可以包括在热处理步骤之后氧化硅膜以产生氧化硅膜的氧化硅膜形成步骤，并且可以包括去除氧化硅膜的氧化硅膜去除步骤。

公开(公告)号：US20100035411A1

公开(公告)日：2010-02-11

申请号：US12444551

申请日：2007-08-13

Applicant: Kazuhiro Fujikawa ,  Takeyoshi Masuda

Inventor： Kazuhiro Fujikawa ,  Takeyoshi Masuda

IPC: H01L21/04

CPC classification number: H01L29/808 ,  H01L21/0465 ,  H01L29/1608 ,  H01L29/66068 ,  H01L29/66901 ,  Y10S438/931

Abstract: A method of manufacturing an SiC semiconductor device includes the steps of ion implanting a dopant at least in a part of a surface of an SiC single crystal, forming an Si film on the surface of the ion-implanted SiC single crystal, and heating the SiC single crystal on which the Si film is formed to a temperature not less than a melting temperature of the Si film.

Abstract translation: 一种制造SiC半导体器件的方法包括以下步骤：在SiC单晶的至少一部分表面上离子注入掺杂剂，在离子注入的SiC单晶的表面上形成Si膜，并加热SiC 在其上形成Si膜的单晶，其温度不低于Si膜的熔融温度。

公开(公告)号：US20080050844A1

公开(公告)日：2008-02-28

申请号：US11664318

申请日：2006-04-02

Applicant: Takeyoshi Masuda

Inventor： Takeyoshi Masuda

IPC: H01L21/00

CPC classification number: C23C16/24 ,  C23C14/185 ,  C30B29/36 ,  C30B33/02

Abstract: A surface reconstruction method for a silicon carbide substrate (1) includes a silicon film forming step of forming a silicon film (2) on a surface of the silicon carbide substrate (1) and a heat treatment step of heat-treating the silicon carbide substrate (1) and the silicon film (2) without providing a polycrystalline silicon carbide substrate on a surface of the silicon film (2). Here, after the heat treatment step, a silicon film removal step of removing the silicon film (2) may be included. Further, a silicon oxide film forming step of oxidizing the silicon film (2) after the heat treatment step to generate a silicon oxide film, and a silicon oxide film removal step of removing the silicon oxide film may-be included.

Abstract translation: 碳化硅衬底（1）的表面重建方法包括在碳化硅衬底（1）的表面上形成硅膜（2）的硅膜形成步骤和对碳化硅衬底（1）进行热处理的热处理步骤 （1）和硅膜（2），而不在硅膜（2）的表面上提供多晶碳化硅衬底。 这里，在热处理步骤之后，可以包括去除硅膜（2）的硅膜去除步骤。 此外，可以包括在热处理步骤之后氧化硅膜（2）的氧化硅膜形成步骤以产生氧化硅膜，并且可以包括去除氧化硅膜的氧化硅膜去除步骤。

公开(公告)号：US06995454B2

公开(公告)日：2006-02-07

申请号：US10354026

申请日：2003-01-30

Applicant: Michio Murata ,  Takeyoshi Masuda

Inventor： Michio Murata ,  Takeyoshi Masuda

IPC: H01L33/00 ,  H01L29/26

CPC classification number: H01S5/0265 ,  H01S5/06226 ,  H01S5/2277

Abstract: A semiconductor optical integrated device 1 comprises a light-emitting element portion 110, modulation element portion 120, and separation portion 130 on a substrate 2. Light-emitting element portion 110 comprises a semiconductor laser element portion, and modulation element portion 120 comprises a modulation element portion. Separation portion 130 is formed between light-emitting element portion 110 and modulation element portion 120. In separation portion 130, a semiconductor embedded portion 80e is provided in a second clad layer 8m. Whereas second clad layer 8m consists of p-type InP, semiconductor embedded portion 80e consists of n-type InP. Hence semiconductor embedded portion 80e has the effect of impeding the leakage current flowing between electrodes 90a and 90b. As a result, the leakage current occurring between electrodes 90a and 90b via second clad layer 8m is reduced.

Abstract translation: 半导体光集成器件1包括基板2上的发光元件部分110，调制元件部分120和分离部分130。 发光元件部分110包括半导体激光元件部分，调制元件部分120包括调制元件部分。 分离部分130形成在发光元件部分110和调制元件部分120之间。 在分离部分130中，半导体嵌入部分80e设置在第二包层8m中。 而第二包层8m由p型InP组成，半导体嵌入部分80e由n型InP组成。 因此，半导体嵌入部分80e具有阻止在电极90a和90b之间流动的漏电流的效果。 结果，经由第二覆盖层8m在电极90a和90b之间产生的漏电流减小。

公开(公告)号：US09000447B2

公开(公告)日：2015-04-07

申请号：US13613838

申请日：2012-09-13

Applicant: Keiji Wada ,  Takeyoshi Masuda ,  Toru Hiyoshi

Inventor： Keiji Wada ,  Takeyoshi Masuda ,  Toru Hiyoshi

IPC: H01L29/15 ,  H01L21/04 ,  H01L29/66 ,  H01L29/04 ,  H01L29/78 ,  H01L29/16 ,  H01L29/423 ,  H01L29/06

CPC classification number: H01L21/0475 ,  H01L21/049 ,  H01L29/045 ,  H01L29/0623 ,  H01L29/1608 ,  H01L29/36 ,  H01L29/4236 ,  H01L29/66068 ,  H01L29/7813

Abstract: A first layer has n type conductivity. A second layer is epitaxially formed on the first layer and having p type conductivity. A third layer is on the second layer and having n type conductivity. ND is defined to represent a concentration of a donor type impurity. NA is defined to represent a concentration of an acceptor type impurity. D1 is defined to represent a location in the first layer away from an interface between the first layer and the second layer in a depth direction. D1 in which 1≦ND/NA≦50 is satisfied is within 1 μm therefrom. A gate trench is provided to extend through the third layer and the second layer to reach the first layer. A gate insulating film covers a side wall of the gate trench. A gate electrode is embedded in the gate trench with the gate insulating film interposed therebetween.

Abstract translation: 第一层具有n型导电性。 第二层外延形成在第一层上并具有p型导电性。 第三层位于第二层上，具有n型导电性。 ND被定义为表示供体型杂质的浓度。 NA被定义为表示受体型杂质的浓度。 D1被定义为在深度方向上表示远离第一层和第二层之间的界面的第一层中的位置。 其中满足1＆nlE; ND / NA＆nlE; 50的D1在其1μm以内。 提供栅极沟槽以延伸穿过第三层和第二层以到达第一层。 栅极绝缘膜覆盖栅极沟槽的侧壁。 栅极电极嵌入栅极沟槽中，栅极绝缘膜插入其间。

公开(公告)号：US08921903B2

公开(公告)日：2014-12-30

申请号：US12517761

申请日：2007-09-21

Applicant: Takeyoshi Masuda ,  Yasuo Namikawa

Inventor： Takeyoshi Masuda ,  Yasuo Namikawa

IPC: H01L29/808 ,  H01L29/66 ,  H01L21/04 ,  H01L29/10 ,  H01L29/16 ,  H01L29/20

CPC classification number: H01L29/808 ,  H01L21/048 ,  H01L29/1066 ,  H01L29/1608 ,  H01L29/2003 ,  H01L29/66901

Abstract: On a p− epitaxial layer, an n-type epitaxial layer and a gate region are formed in this order. A gate electrode is electrically connected to the gate region, and a source electrode and a drain electrode are spaced apart from each other with the gate electrode sandwiched therebetween. A control electrode is used for applying to the p− epitaxial layer a voltage that causes a reverse biased state of the p− epitaxial layer and the n-type epitaxial layer in an OFF operation.

Abstract translation: 在p-外延层上依次形成n型外延层和栅极区。 栅电极电连接到栅极区，源电极和漏极彼此间隔开，栅电极夹在其间。 控制电极被用于向p-外延层施加一个电压，该电压导致p型外延层和n型外延层在OFF操作中的反向偏压状态。

公开(公告)号：US08796123B2

公开(公告)日：2014-08-05

申请号：US13489152

申请日：2012-06-05

Applicant: Shunsuke Yamada ,  Takeyoshi Masuda

Inventor： Shunsuke Yamada ,  Takeyoshi Masuda

IPC: H01L21/425

CPC classification number: H01L29/7802 ,  H01L21/0465 ,  H01L21/31116 ,  H01L29/1608 ,  H01L29/518 ,  H01L29/66068

Abstract: An impurity of a first conductivity type is implanted onto a silicon carbide substrate through an opening in a mask layer. First and second films made of first and second materials respectively are formed. It is sensed that etching of the first material is performed during anisotropic etching, and then anisotropic etching is stopped. An impurity of a second conductivity type is implanted onto the silicon carbide substrate through the opening narrowed by the first and second films. Thus, the impurity regions can be formed in an accurately self-aligned manner.

Abstract translation: 通过掩模层中的开口将第一导电类型的杂质注入到碳化硅衬底上。 分别形成由第一和第二材料制成的第一和第二薄膜。 感测到在各向异性蚀刻期间进行第一材料的蚀刻，然后停止各向异性蚀刻。 通过第一和第二薄膜变窄的开口将第二导电类型的杂质注入到碳化硅衬底上。 因此，可以精确地自对准地形成杂质区域。

公开(公告)号：US08609521B2

公开(公告)日：2013-12-17

申请号：US13583564

申请日：2011-11-07

Applicant: Ryosuke Kubota ,  Keiji Wada ,  Takeyoshi Masuda ,  Hiromu Shiomi

Inventor： Ryosuke Kubota ,  Keiji Wada ,  Takeyoshi Masuda ,  Hiromu Shiomi

IPC: H01L21/265

CPC classification number: H01L29/7802 ,  H01L21/046 ,  H01L21/268 ,  H01L29/1608 ,  H01L29/66068

Abstract: A silicon carbide substrate having a surface is prepared. An impurity region is formed by implanting ions from the surface into the silicon carbide substrate. Annealing for activating the impurity region is performed. The annealing includes the step of applying first laser light having a first wavelength to the surface of the silicon carbide substrate, and the step of applying second laser light having a second wavelength to the surface of the silicon carbide substrate. The silicon carbide substrate has first and second extinction coefficients at the first and second wavelengths, respectively. A ratio of the first extinction coefficient to the first wavelength is higher than 5×105/m. A ratio of the second extinction coefficient to the second wavelength is lower than 5×105/m. Consequently, damage to the surface of the silicon carbide substrate during laser annealing can be reduced.

Abstract translation: 制备具有表面的碳化硅衬底。 通过从表面注入离子到碳化硅衬底中形成杂质区。 执行用于激活杂质区域的退火。 退火包括将具有第一波长的第一激光施加到碳化硅衬底的表面的步骤，以及将具有第二波长的第二激光施加到碳化硅衬底的表面的步骤。 碳化硅衬底分别在第一和第二波长处具有第一和第二消光系数。 第一消光系数与第一波长的比率高于5×10 5 / m。 第二消光系数与第二波长的比率低于5×10 5 / m。 因此，可以减少在激光退火期间对碳化硅衬底的表面的损坏。

公开(公告)号：US08436366B2

公开(公告)日：2013-05-07

申请号：US13131369

申请日：2010-04-06

Applicant: Shin Harada ,  Makoto Sasaki ,  Takeyoshi Masuda

Inventor： Shin Harada ,  Makoto Sasaki ,  Takeyoshi Masuda

IPC: H01L29/15 ,  H01L29/04

CPC classification number: H01L29/7802 ,  B24B7/17 ,  B24B7/228 ,  B24B37/08 ,  B24B37/10 ,  C30B25/20 ,  C30B29/36 ,  H01L21/02378 ,  H01L21/0243 ,  H01L21/02529 ,  H01L21/0465 ,  H01L29/02 ,  H01L29/045 ,  H01L29/063 ,  H01L29/0657 ,  H01L29/1608 ,  H01L29/66068 ,  H01L29/78 ,  H01L29/7813 ,  H01L29/808 ,  H01L29/8083 ,  H01L29/812 ,  H01L29/8122 ,  H01L29/8128 ,  H01L29/8611 ,  H01L29/872

Abstract: A substrate achieving suppressed deterioration of processing accuracy of a semiconductor device due to bending of the substrate, a substrate with a thin film and a semiconductor device formed with the substrate above, and a method of manufacturing the semiconductor device above are obtained. A substrate according to the present invention has a main surface having a diameter of 2 inches or greater, a value for bow at the main surface being not smaller than −40 μm and not greater than −5 μm, and a value for warp at the main surface being not smaller than 5 μm and not greater than 40 μm. Preferably, a value for surface roughness Ra of the main surface of the substrate is not greater than 1 nm and a value for surface roughness Ra of a main surface is not greater than 100 nm.

Abstract translation: 获得由于基板的弯曲，具有薄膜的基板和形成有上述基板的半导体器件导致的半导体器件的加工精度的抑制劣化的基板以及上述制造半导体器件的方法。 根据本发明的基底具有直径为2英寸或更大的主表面，主表面的弓形值不小于-40μm且不大于-5μm，并且在该表面处的翘曲值 主表面不小于5μm，不大于40μm。 优选地，基板的主表面的表面粗糙度Ra的值不大于1nm，并且主表面的表面粗糙度Ra的值不大于100nm。