公开(公告)号：US10192985B2

公开(公告)日：2019-01-29

申请号：US14805450

申请日：2015-07-21

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Cheng-Ta Wu ,  Ting-Chun Wang ,  Wei-Ming You ,  J. W. Wu

IPC: H01L29/78 ,  H01L29/417 ,  H01L29/66 ,  H01L29/06 ,  H01L21/265 ,  H01L21/324

Abstract: A method for manufacturing a semiconductor device is provided including forming one or more fins over a substrate and forming an isolation insulating layer over the one or more fins. A dopant is introduced into the isolation insulating layer. The isolation insulating layer containing the dopant is annealed, and a portion of the oxide layer is removed so as to expose a portion of the fins.

公开(公告)号：US20170250282A1

公开(公告)日：2017-08-31

申请号：US15054133

申请日：2016-02-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Ta Wu ,  Yu-Ting Lin ,  Po-Kai Hsiao ,  Po-Kang Ho ,  Ting-Chun Wang

IPC: H01L29/78 ,  H01L21/8234 ,  H01L27/088

CPC classification number: H01L29/7848 ,  H01L21/823431 ,  H01L21/823468 ,  H01L21/823481 ,  H01L27/0886 ,  H01L29/165 ,  H01L29/66545

Abstract: A FinFET including a substrate, a plurality of isolation structures, a plurality of blocking layers, and a gate stack is provided. The substrate has a plurality of semiconductor fins. The isolation structures are located on the substrate to isolate the semiconductor fins. In addition, the semiconductor fins protrude from the isolation structures. The blocking layers are located between the isolation structures and the semiconductor fins. The material of the blocking layers is different from the material of the isolation structures. The gate stack is disposed across portions of the semiconductor fins, portions of the blocking layers and portions of the isolation structures. In addition, a method for fabricating the FinFET is also provided.

公开(公告)号：US20150357421A1

公开(公告)日：2015-12-10

申请号：US14745600

申请日：2015-06-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： I-Che Huang ,  Pu-Fang Chen ,  Ting-Chun Wang

IPC: H01L29/32 ,  H01L21/67 ,  H01L29/16

CPC classification number: H01L29/32 ,  C30B29/06 ,  H01L21/3225 ,  H01L21/324 ,  H01L21/67098 ,  H01L21/67288 ,  H01L22/12 ,  H01L29/16 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Some embodiments relate to a silicon wafer having a disc-like silicon body. The wafer includes a central portion circumscribed by a circumferential edge region. A plurality of sampling locations, which are arranged in the circumferential edge region, have a plurality of wafer property values, respectively, which correspond to a wafer property. The plurality of wafer property values differ from one another according to a pre-determined statistical edge region profile.

Abstract translation: 一些实施例涉及具有盘状硅体的硅晶片。 晶片包括由圆周边缘区域限定的中心部分。 布置在圆周边缘区域中的多个采样位置分别具有对应于晶片特性的多个晶片特性值。 多个晶片特性值根据预定的统计边缘区域轮廓彼此不同。